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52447 Commits

Author SHA1 Message Date
David Blaikie
49c0a9ac98 Remove dead code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148206 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-15 01:09:13 +00:00
Craig Topper
799ea5ccc0 Truncate of undef is just undef of smaller size. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148205 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-15 01:05:11 +00:00
Craig Topper
d07ef50ca1 Fix the memop type on a couple 256-bit AVX instructions that were using f128mem instead of f256mem. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148196 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-14 18:29:57 +00:00
Craig Topper
446626d236 Add a bunch of AVX instructions to the folding tables. Also fixed the alignment on 256-bit AVX2 instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148194 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-14 18:14:53 +00:00
Duncan Sands
c464e998e6 Speculatively revert commit 148175 (rafael), to see if this fixes 
non-determinism in the 32 bit dragonegg buildbot.  Original commit
message:
Only emit the Leh_func_endN symbol when needed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148191 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-14 17:16:48 +00:00
Andrew Trick
dd1f22f25d Fix a corner case hit by redundant phi elimination running after LSR. 
Fixes PR11761: bad IR w/ redundant Phi elim


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148177 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-14 03:17:23 +00:00
Rafael Espindola
da22344804 Only emit the Leh_func_endN symbol when needed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148175 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-14 02:36:51 +00:00
Andrew Trick
3c58ba8ea7 misched: Initial code for building an MI level scheduling DAG 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148174 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-14 02:17:18 +00:00
Andrew Trick
7ebcaf4cf9 Move physreg dependency generation into aptly named addPhysRegDeps. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148173 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-14 02:17:15 +00:00
Andrew Trick
5e920d7c83 misched: Added ScheduleDAGInstrs::IsPostRA 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148172 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-14 02:17:12 +00:00
Andrew Trick
e9ef4ed13b misched: Invoke the DAG builder on each sequence of schedulable instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148171 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-14 02:17:09 +00:00
Andrew Trick
5edf2f03d5 Move things around to make the file navigable, even though it will probably be split up later. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148170 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-14 02:17:06 +00:00
Evan Cheng
bfe8afaaec After r147827 and r147902, it's now possible for unallocatable registers to be 
live across BBs before register allocation. This miscompiled 197.parser
when a cmp + b are optimized to a cbnz instruction even though the CPSR def
is live-in a successor.
        cbnz    r6, LBB89_12
...
LBB89_12:
        ble     LBB89_1

The fix consists of two parts. 1) Teach LiveVariables that some unallocatable
registers might be liveouts so don't mark their last use as kill if they are.
2) ARM constantpool island pass shouldn't form cbz / cbnz if the conditional
branch does not kill CPSR.

rdar://10676853


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148168 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-14 01:53:46 +00:00
Chad Rosier
d32d3b758f Fix pasto from r146196. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148167 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-14 01:50:21 +00:00
Dan Gohman
92180988a4 Fix an unused variable warning that Chad noticed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148164 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-14 00:47:44 +00:00
Rafael Espindola
54f7533e36 Remove previous commit while I debug the bot failures. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148156 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-13 23:28:50 +00:00
Jakob Stoklund Olesen
ece8b73eb2 Use RegisterTuples to generate pseudo-registers. 
The QQ and QQQQ registers are not 'real', they are pseudo-registers used
to model some vld and vst instructions.

This makes the call clobber lists longer, but I intend to get rid of
those soon.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148151 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-13 22:55:42 +00:00
Rafael Espindola
cf05d03961 Remove label that is not used anymore. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148150 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-13 22:41:58 +00:00
Eli Friedman
09a536a88b Speculatively revert r148132+r148133 to try and fix a buildbot failure. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148149 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-13 22:34:39 +00:00
Andrew Trick
23d1c5ce8a Remove pointless mode line in .cpp file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148143 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-13 22:04:16 +00:00
Devang Patel
85d5aaecd0 Revert r148131, it was committed before it was ready. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148134 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-13 19:28:58 +00:00
Stepan Dyatkovskiy
5dab2bf293 Cosmetic patch for r148132. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148133 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-13 19:27:22 +00:00
Stepan Dyatkovskiy
a5a1e46d00 LoopUnswitch: All helper data that is collected during loop-unswitch iterations was moved to separated class (LUAnalysisCache). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148132 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-13 19:13:54 +00:00
Devang Patel
c798cc4283 Refactor. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148131 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-13 19:12:18 +00:00
Craig Topper
0518970dc8 Convert SHUFPD with the same register for both sources to PSHUFD if it would prevent a register copy. Similar to SHUFPS, but requires the mask to be converted. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148112 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-13 09:21:41 +00:00
Craig Topper
562659ff6b use v8i32 as optimal mem type over v8f32 if AVX2 is enabled. Similar to SSE2 vs SSE1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148109 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-13 08:32:21 +00:00
Craig Topper
12216172c0 Make X86 instruction selection use 256-bit VPXOR for build_vector of all ones if AVX2 is enabled. This gives the ExeDepsFix pass a chance to choose FP vs int as appropriate. Also use v8i32 as the type for getZeroVector if AVX2 is enabled. This is consistent with SSE2 using prefering v4i32. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148108 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-13 08:12:35 +00:00
Craig Topper
c30432ab57 Add patterns for v16i16 and v32i8 immAllZerosV to select VPXOR to match v4i64 and v8i32. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148106 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-13 06:59:47 +00:00
Andrew Trick
96f678f2d7 Added the MachineSchedulerPass skeleton. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148105 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-13 06:30:30 +00:00
Andrew Trick
524ff020f3 wrong filename 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148103 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-13 06:30:22 +00:00
Andrew Trick
07680ec7a1 80-col violation 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148102 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-13 06:30:19 +00:00
Craig Topper
b9c7f652d7 Use 8i32 constant pool entry for converting AVX2_SETALLONES. Possibly fixes PR11750. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148101 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-13 06:12:41 +00:00
Craig Topper
e6cf4a070d Fix typo in PerformAddCombine that caused any vector type to be checked for horizontal add/sub if AVX2 is enabled. This caused an assert to fail for non 128/256-bit vectors when done before type legalizing. Fixes PR11749. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148096 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-13 05:04:25 +00:00
Jakob Stoklund Olesen
8dd6f0c835 Delete CodeInit and CodeRecTy from TableGen. 
The code type was always identical to a string anyway. Now it is simply
a synonym. The code literal syntax [{...}] is still valid.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148092 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-13 03:38:34 +00:00
Jakob Stoklund Olesen
ebaf92c67d Use uniqued StringInit pointers for lookups. 
This avoids a gazillion StringMap and dynamic_cast calls, making
TableGen run 3x faster.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148091 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-13 03:16:35 +00:00
Evan Cheng
c4b527ac06 DAGCombine's logic for forming pre- and post- indexed loads / stores were being 
overly conservative. It was concerned about cases where it would prohibit
folding simple [r, c] addressing modes. e.g.
  ldr r0, [r2]
  ldr r1, [r2, #4]
=>
  ldr r0, [r2], #4
  ldr r1, [r2]
Change the logic to look for such cases which allows it to form indexed memory
ops more aggressively.

rdar://10674430


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148086 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-13 01:37:24 +00:00
Bill Wendling
b4ee5168ab Fix off-by-one error. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148077 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-13 00:41:53 +00:00
Dan Gohman
79522dc569 Implement proper ObjC ARC objc_retainBlock "escape" analysis, so that 
the optimizer doesn't eliminate objc_retainBlock calls which are needed
for their side effect of copying blocks onto the heap.
This implements rdar://10361249.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148076 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-13 00:39:07 +00:00
Pete Cooper
ddfda5cd16 Added MVT::v2f16 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148067 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-12 23:14:13 +00:00
Bill Wendling
bf5b13d07e Revert accidental commit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148065 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-12 23:06:28 +00:00
Bill Wendling
86b1a7d614 Fix the code that was WRONG. 
The registers are placed into the saved registers list in the reverse order,
which is why the original loop was written to loop backwards.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148064 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-12 23:05:03 +00:00
Pete Cooper
d578b905de Added FPOW, FEXP, FLOG to PromoteNode so that custom actions can be set to Promote for those operations. 
Sorry, no test case yet


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148050 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-12 21:46:18 +00:00
Elena Demikhovsky
16db710898 Fixed a bug in LowerVECTOR_SHUFFLE caused assertion failure 
lc: X86ISelLowering.cpp:6480: llvm::SDValue llvm::X86TargetLowering::LowerVECTOR_SHUFFLE(llvm::SDValue, llvm::SelectionDAG&) const: Assertion `V1.getOpcode() != ISD::UNDEF&&  "Op 1 of shuffle should not be undef"' failed.
Added a test.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148044 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-12 20:33:10 +00:00
Evan Cheng
c16c25fbc3 When hoisting common code, watch out for uses which are marked "kill". If the 
killed registers are needed below the insertion point, then unset the kill
marker.

Sorry I'm not able to find a reduced test case.

rdar://10660944


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148043 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-12 20:31:24 +00:00
Rafael Espindola
85b9d43d4c Support segmented stacks on 64-bit FreeBSD. 
This patch uses tcb_spare field in the tcb structure to store info.
Patch by Jyun-Yan You.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148041 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-12 20:24:30 +00:00
Rafael Espindola
e4d18de5d1 Support segmented stacks on win32. 
Uses the pvArbitrary slot of the TIB, which is reserved for applications. We
only support frames with a static size.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148040 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-12 20:22:08 +00:00
Evan Cheng
f0a95356d6 Allow targets to select source order pre-RA scheduler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148033 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-12 18:27:52 +00:00
Devang Patel
dd929fc704 Rename X86ATTAsmParser -> X86AsmParser 
We are using one parser to parse att as well as intel style syntax.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148032 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-12 18:03:40 +00:00
Jakob Stoklund Olesen
b20b518f80 Make SplitAnalysis::UseSlots private. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148031 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-12 17:53:44 +00:00
Benjamin Kramer
e2eb92578a After Jakob's r147938 exception handling on i386 was completely broken. 
Restore the (obviously wrong) behavior from before r147938 without relying on
undefined behavior. Add a fat FIXME note.

This should fix nightly tester failures.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148030 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-12 17:37:18 +00:00