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6856 Commits

Author SHA1 Message Date
Evan Cheng
8ca29326e1 Don't dag combine floating point select to max and min intrinsics. Those 
take v4f32 / v2f64 operands and may end up causing larger spills / restores.
Added X86 specific nodes X86ISD::FMAX, X86ISD::FMIN instead.

This fixes PR996.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31645 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-10 21:43:37 +00:00
Evan Cheng
d6373bcd82 Fix a bug in SelectScalarSSELoad. Since the load is wrapped in a 
SCALAR_TO_VECTOR, even if the hasOneUse() check pass we may end up folding
the load into two instructions. Make sure we check the SCALAR_TO_VECTOR
has only one use as well.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31641 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-10 21:23:04 +00:00
Chris Lattner
6a944e2592 dform 8/9 are identical to dform 1 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31637 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-10 17:51:02 +00:00
Evan Cheng
50b3b50cd0 Fix a potential bug. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31634 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-10 09:13:37 +00:00
Evan Cheng
438f7bc67c Add implicit def / use operands to MachineInstr. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31633 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-10 08:43:01 +00:00
Chris Lattner
4eab71497d add an initial cut at preinc loads for ppc32. This is broken for ppc64 
(because the 64-bit reg target versions aren't implemented yet), doesn't
support r+r addr modes, and doesn't handle stores, but it works otherwise. :)

This is disabled unless -enable-ppc-preinc is passed to llc for now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31621 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-10 02:08:47 +00:00
Chris Lattner
26ddb506ec add note about ugly codegen with preinc 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31617 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-10 01:33:53 +00:00
Evan Cheng
171d09ea53 Use TargetInstrInfo::getNumOperands() instead of MachineInstr::getNumOperands(). In preparation for implicit reg def/use changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31616 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-10 01:28:43 +00:00
Anton Korobeynikov
df78611726 Fixing PR990: http://llvm.org/PR990. 
This should unbreak csretcc on Linux & mingw targets. Several tests from
llvm-test should be also restored (fftbench, bigfib).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31613 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-10 00:48:11 +00:00
Chris Lattner
578d2df84b add a note about viterbi 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31612 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-10 00:23:26 +00:00
Evan Cheng
cd63319227 PPC supports i32 / i64 pre-inc load / store. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31599 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-09 19:11:50 +00:00
Evan Cheng
0030582239 Rename ISD::MemOpAddrMode to ISD::MemIndexedMode 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31596 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-09 18:44:21 +00:00
Evan Cheng
144d8f09e1 Rename ISD::MemOpAddrMode to ISD::MemIndexedMode 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31595 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-09 17:55:04 +00:00
Rafael Espindola
f819a4999a implement load effective address similar to the alpha backend 
remove lea_addri and the now unused memri addressing mode


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31592 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-09 13:58:55 +00:00
Evan Cheng
a1fd6504aa Remove M_2_ADDR_FLAG. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31583 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-09 02:22:54 +00:00
Evan Cheng
81fd60722a Added indexed store node and patfrag's. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31576 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-08 23:02:11 +00:00
Evan Cheng
aacf99964f Use movl+xchgl instead of pushl+popl. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31572 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-08 20:35:37 +00:00
Evan Cheng
0d53826f36 Match tblegen changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31571 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-08 20:34:28 +00:00
Rafael Espindola
6e8c6493f0 initial implementation of addressing mode 2 
TODO: fix lea_addri


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31552 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-08 17:07:32 +00:00
Reid Spencer
3822ff5c71 For PR950: 
This patch converts the old SHR instruction into two instructions,
AShr (Arithmetic) and LShr (Logical). The Shr instructions now are not
dependent on the sign of their operands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31542 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-08 06:47:33 +00:00
Chris Lattner
fc5b1ab949 Refactor all the addressing mode selection stuff into the isel lowering 
class, where it can be used for preinc formation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31536 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-08 02:15:41 +00:00
Chris Lattner
302bf9c973 correct the (currently unused) pattern for lwzu. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31535 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-08 02:13:12 +00:00
Evan Cheng
6e56e2c602 Fixed a bug which causes x86 be to incorrectly match 
shuffle v, undef, <2, ?, 3, ?>
to movhlps
It should match to unpckhps instead.

Added proper matching code for
shuffle v, undef, <2, 3, 2, 3>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31519 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-07 22:14:24 +00:00
Chris Lattner
6e11295b23 add a note from viterbi 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31506 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-07 18:30:21 +00:00
Chris Lattner
0921365b88 fix encoding of BLR 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31485 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-07 01:51:50 +00:00
Chris Lattner
8c97c07040 add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31477 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-06 21:26:49 +00:00
Jeff Cohen
d41b30def3 Unbreak VC++ build. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31464 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-05 19:31:28 +00:00
Reid Spencer
bcf81242df Fix a bug in the last patch and convert to && instead of & for logical expr. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31463 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-05 19:26:37 +00:00
Reid Spencer
7c475c5d12 Implement the -enabled-cbe-printf-a feature. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31462 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-05 17:09:41 +00:00
Chris Lattner
6fc40079f3 encode BLR predicate info for the JIT 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31450 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-04 05:42:48 +00:00
Chris Lattner
af53a87052 Go through all kinds of trouble to mark 'blr' as having a predicate operand 
that takes a register and condition code.  Print these pieces of BLR the
right way, even though it is currently set to 'always'.

Next up: get the JIT encoding right, then enhance branch folding to produce
predicated blr for simple examples.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31449 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-04 05:27:39 +00:00
Chris Lattner
0638b260dc Describe PPC predicates, which are a pair of CR# and condition. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31438 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-03 23:53:25 +00:00
Chris Lattner
60a09a5d6d initial steps to getting the predicate on PPC::BLR right. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31437 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-03 23:52:18 +00:00
Chris Lattner
e69c436e6f remove dead var 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31436 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-03 23:50:15 +00:00
Chris Lattner
3751844b39 remove dead/redundant vars 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31435 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-03 23:48:56 +00:00
Chris Lattner
56fe5276ef remove redundant/dead vars 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31434 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-03 23:47:20 +00:00
Chris Lattner
7049540de5 remove dead vars 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31433 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-03 23:46:45 +00:00
Chris Lattner
d7c628de89 add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31429 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-03 22:27:39 +00:00
Rafael Espindola
f05696c1b5 revert previous patch 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31411 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-03 03:08:28 +00:00
Evan Cheng
bdd371c0ed Dead code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31405 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-03 02:08:41 +00:00
Rafael Espindola
115bfcb574 add createCFGSimplificationPass to ARMTargetMachine::addInstSelector 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31400 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-03 01:39:25 +00:00
Chris Lattner
6f51a77827 silence warning 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31395 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-03 01:19:31 +00:00
Chris Lattner
1331dec131 silence warnings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31394 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-03 01:18:29 +00:00
Chris Lattner
15092547e4 silence warning 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31393 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-03 01:13:15 +00:00
Chris Lattner
9c5d4de837 silence warnings 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31392 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-03 01:11:05 +00:00
Reid Spencer
3a717d522f Make CBackend -pedantic clean. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31388 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-03 00:00:57 +00:00
Chris Lattner
4d5c0014b6 fix a bug reid noticed 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31385 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-02 23:39:53 +00:00
Reid Spencer
3ed469ccd7 For PR786: 
Turn on -Wunused and -Wno-unused-parameter. Clean up most of the resulting
fall out by removing unused variables. Remaining warnings have to do with
unused functions (I didn't want to delete code without review) and unused
variables in generated code. Maintainers should clean up the remaining
issues when they see them. All changes pass DejaGnu tests and Olden.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31380 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-02 20:25:50 +00:00
Rafael Espindola
e931a37a4e move ARMCondCodeToString to ARMAsmPrinter.cpp 
remove unused variables from lowerCall


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31378 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-02 15:00:02 +00:00
Andrew Lenharth
d079cdb6d3 fix 2006-11-01-vastart.ll 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31371 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-02 03:05:26 +00:00