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11857 Commits

Author SHA1 Message Date
Bob Wilson
0cedab9a0d Neon does not actually have VLD{234}.64 instructions. 
These operations will have to be synthesized from other instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78263 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-06 00:24:27 +00:00
Bob Wilson
70cd88fb7b Add a new pre-allocation pass to assign adjacent registers for Neon instructions 
that have that constraint.  This is currently just assigning a fixed set of
registers, and it only handles VLDn for n=2,3,4 with DPR registers.
I'm going to expand it to handle more operations next; we can make it smarter
once everything is working correctly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78256 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 23:12:45 +00:00
Anton Korobeynikov
b5e0172405 Better handle kernel code model. Also, generalize the things and fix one 
subtle bug with small code model.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78255 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 23:01:26 +00:00
Dan Gohman
59e34921a5 Use GR32 for copies between GR32_NOSP and GR32_NOREX, as neither 
is a subset of the other, but both are subsets of GR32.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78250 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 22:18:26 +00:00
David Goodwin
7bfdca0206 When using NEON for single-precision FP, the NEON result must be placed in D0-D15 as these are the only D registers with S subregs. Introduce a new regclass to represent D0-D15 and use it in the NEON single-precision FP patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78244 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 21:02:22 +00:00
Chris Lattner
cafbdc5c09 remove the 'DataSectionStartSuffix' and 'TextSectionStartSuffix' knobs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78242 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 20:49:52 +00:00
Anton Korobeynikov
058c251d4a Remove redundand checks: the only way to have, e.g. f32 RegVT is exactly 
hardfloat case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78237 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 20:15:19 +00:00
Dan Gohman
be0cf7dbc2 hasSuperClass tests for a strict superset relation, rather than 
a superset relation. This code wants to test the regular superset
relation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78236 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 20:13:45 +00:00
Anton Korobeynikov
14d9495403 Unbreak the stuff, this is ugly, but we cannot do better for now with 'plain' C calling conv. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78232 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 19:40:16 +00:00
Anton Korobeynikov
567d14f07c Missed pieces for ARM HardFP ABI. 
Patch by Sandeep Patel!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78225 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 19:04:42 +00:00
Andrew Lenharth
7f285c8024 Use elf Object File directly 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78220 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 18:13:04 +00:00
Daniel Dunbar
e22f4da01d Remove some dead code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78219 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 18:12:37 +00:00
Dan Gohman
74f6f9a931 Enable the new no-SP register classes by default. This is to address 
PR4572. A few tests have some minor code regressions due to different
coalescing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78217 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 17:40:24 +00:00
Bob Wilson
7f0f2515a0 Remove a redundant declaration. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78216 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 17:39:44 +00:00
Anton Korobeynikov
9e155d61da Convert bswap test to filecheck, add more test entries & convert stuff to filecheck 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78212 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 16:50:53 +00:00
Dan Gohman
22f7d57dde Fix a bug in the PIC16 backend. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78211 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 16:46:43 +00:00
David Goodwin
ce3c1f2a0e Disable NEON single-precision FP support for Cortex-A8, for now... 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78209 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 16:40:57 +00:00
Devang Patel
bccdcb1857 Remove dead code. MDNode and MDString are not Constant anymore. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78207 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 16:40:02 +00:00
Anton Korobeynikov
93e21f7b6f Add memory versions of some instructions. 
Patch by Neale Ferguson!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78203 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 16:16:11 +00:00
David Goodwin
1f0e404c87 By default, for cortex-a8 use NEON for single-precision FP. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78200 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 16:01:19 +00:00
Anton Korobeynikov
1e0039d6cf Special constants as destinations does not work as expected - drop the patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78191 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 14:42:00 +00:00
Andrew Lenharth
1ad11a896c Alpha: Get section directives right 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78189 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 13:59:57 +00:00
Anton Korobeynikov
0802a1e1e8 Cleanup in dbg_stoppoint handling in CBE. Patch by Sandeep Patel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78182 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 09:31:40 +00:00
Anton Korobeynikov
e392c8336f Minor arm CBE fixes. Patch by Sandeep. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78181 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 09:31:07 +00:00
Anton Korobeynikov
e641b527e8 Emit module-level inline asm for CBE. 
Patch by Sandeep Patel

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78180 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 09:29:56 +00:00
Bruno Cardoso Lopes
52d0851446 - Remove custom handling of jumptables by the elf writter (this was 
a dirty hack and isn't need anymore since the last x86 code emitter patch)
- Add a target-dependent modifier to addend calculation
- Use R_X86_64_32S relocation for X86::reloc_absolute_word_sext
- Use getELFSectionFlags whenever possible
- fix getTextSection to use TLOF and emit the right text section 
- Handle global emission for static ctors, dtors and Type::PointerTyID
- Some minor fixes



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78176 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 06:57:03 +00:00
Evan Cheng
61f4b721b2 80 col violations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78175 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 06:41:25 +00:00
Dan Gohman
c3c9c486e4 Teach X86FastISel how to handle CCValAssign::BCvt, which is used for 
MMX arguments. This fixes PR4684.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78163 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 05:33:42 +00:00
Chris Lattner
26d054d903 Clarify common linkage and the requirements on it. Enforce 
them in the verifier.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78160 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 05:21:07 +00:00
Chris Lattner
58bed8fc29 expose SectionKindForGlobal to curious clients, named as 
getKindForGlobal.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78156 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 04:25:40 +00:00
Bob Wilson
aa289d5e7f Oops. I didn't mean to commit this piece yet. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78146 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 02:47:13 +00:00
Dan Gohman
98ca4f2a32 Major calling convention code refactoring. 
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.

This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.

This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78142 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 01:29:28 +00:00
Dan Gohman
5b0d72e850 Remove an unnecessary flush in the CppBackend's output. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78138 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 01:06:38 +00:00
Dan Gohman
1c55fab534 Don't flush the raw_ostream between each MachineFunction. These flush 
calls were originally put in place because errs() at one time was
not unbuffered, and these print routines are commonly used with errs()
for debugging. However, errs() is now properly unbuffered, so the
flush calls are no longer needed. This significantly reduces the
number of write(2) calls for regular asm printing when there are many
small functions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78137 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 00:49:25 +00:00
Bob Wilson
4a3d35abef Change DAG nodes for Neon VLD2/3/4 operations to return multiple results. 
Get rid of yesterday's code to fix the register usage during isel.
Select the new DAG nodes to machine instructions.  The new pre-alloc pass
to choose adjacent registers for these results is not done, so the
results of this will generally not assemble yet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78136 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 00:49:09 +00:00
Bruno Cardoso Lopes
e55fef36a9 1) Proper emit displacements for x86, using absolute relocations where necessary 
for ELF to work.  
2) RIP addressing: Use SIB bytes for absolute relocations where RegBase=0, 
IndexReg=0.
3) The JIT can get the real address of cstpools and jmptables during
code emission, fix that for object code emission


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78129 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 00:11:21 +00:00
Evan Cheng
35d6c41fde Fix part 1 of pr4682. PICADD is a 16-bit instruction even in thumb2 mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78126 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-04 23:47:55 +00:00
Bob Wilson
c00479253b Replace dregsingle operand modifier with explicit escaped curly brackets. 
For other VLDn and VSTn operations, we need to list the multiple registers
explicitly anyway, so there's no point in special-casing this one usage.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78109 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-04 21:39:33 +00:00
Mike Stump
4dcff6db72 Restlyize to match other targets, fixes cmake build to boot. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78105 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-04 21:27:06 +00:00
Evan Cheng
9e7a312391 Enable load / store multiple pass for Thumb2. It's not using ldrd / strd yet. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78104 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-04 21:12:13 +00:00
Chris Lattner
275bb1bd12 remove a random reference to subtarget. Even without this, we 
still get "intel syntax" instructions from llc with  
-x86-asm-syntax=intel




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78103 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-04 21:12:08 +00:00
David Goodwin
53e4471adc Add NEON single-precision FP support for fabs and fneg. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78101 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-04 20:39:05 +00:00
Chris Lattner
f9c1ccf280 rip out SectionEndDirectiveSuffix support, only uses by 
the masm backend.  If anyone cares about masm in the future,
we'll have semantic sections it can hang off of.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78096 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-04 20:09:41 +00:00
Jakob Stoklund Olesen
71d342e854 Most flags are reserved registers on Blackfin. 
The only exception is CC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78089 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-04 19:16:55 +00:00
Evan Cheng
3425df44b5 In thumb mode, r7 is used as frame register. This fixes pr4681. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78086 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-04 18:46:17 +00:00
David Goodwin
b84f3d427c Match common pattern for FNMAC. Add NEON SP support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78085 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-04 18:44:29 +00:00
Sanjiv Gupta
ada097a853 Legalize i64 store operations generated by inst-combine. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78082 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-04 17:59:16 +00:00
David Goodwin
42a83f2d15 Initial support for single-precision FP using NEON. Added "neonfp" attribute to enable. Added patterns for some binary FP operations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78081 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-04 17:53:06 +00:00
Daniel Dunbar
7145e9be64 Avoid compiler warning (in -Asserts mode) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78070 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-04 16:46:12 +00:00
Chris Lattner
ec409759e9 enhance codegen to put 16-bit character strings into the 
__TEXT,__ustring section on darwin.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78068 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-04 16:27:13 +00:00