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210 Commits

Author SHA1 Message Date
Chris Lattner
4e624ecd07 don't crash when running the PPC backend on non-ppc hosts without specifying 
a subtarget.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22677 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-05 16:17:22 +00:00
Nate Begeman
3d72d14887 Use the new subtarget support to automatically choose the correct ABI 
and asm printer for PowerPC if one is not specified.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22659 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-04 20:49:48 +00:00
Nate Begeman
8c00f8cdc7 Add Subtarget support to PowerPC. Next up, using it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22644 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-04 07:12:09 +00:00
Jeff Cohen
00b16889ab Eliminate all remaining tabs and trailing spaces. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22523 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-07-27 06:12:32 +00:00
Nate Begeman
2497e6391f Support building non-PIC 
Remove the LoadHiAddr pseudo-instruction.
Optimization of stores to and loads from statics.
Force JIT to use new non-PIC codepaths.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22494 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-07-21 20:44:43 +00:00
Chris Lattner
2130c08930 revert to using 4-byte alignment for doubles, as specified by the ABI 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22493 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-07-21 19:17:18 +00:00
Nate Begeman
adeb43ddf4 Generate mfocrf when targeting g5. Generate fsqrt/fsqrts when targetin g5. 
8-byte align doubles.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22486 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-07-20 22:42:00 +00:00
Nate Begeman
a3fd400fa8 Integrate SelectFPExpr into SelectExpr. This gets PPC32 closer to being 
automatically generated from a target description.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22470 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-07-19 16:51:05 +00:00
Chris Lattner
0431c96cec Refactor the addPassesToEmitAssembly interface into a addPassesToEmitFile 
interface.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22282 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-06-25 02:48:37 +00:00
Misha Brukman
b5f662fa03 Remove trailing whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21425 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-21 23:30:14 +00:00
Nate Begeman
f8b02949e3 Make pattern isel default for ppc 
Add new ppc beta option related to using condition registers
Make pattern isel control flag (-enable-pattern-isel) global and tristate
  0 == off
  1 == on
  2 == target default


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21309 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-15 22:12:16 +00:00
Nate Begeman
d3e6b94020 Remove 64 bit simple ISel, it never worked correctly 
Add initial (buggy) implementation of 64 bit pattern ISel


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21096 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-05 08:51:15 +00:00
Nate Begeman
5e9666129a Implement more of the PPC32 Pattern ISel: 
1) dynamic stack alloc
2) loads
3) shifts
4) subtract
5) immediate form of add, and, or, xor
6) change flag from -pattern-isel to -enable-ppc-pattern-isel

Remove dead arguments from getGlobalBaseReg in the simple ISel


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20810 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-03-24 06:28:42 +00:00
Nate Begeman
a9795f81e9 Addition of the PPC32 Pattern ISel. While it is far from complete, it will 
be brought up to parity with the current simple ISel in the coming days.
Currently, -pattern-isel is required to trigger it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20805 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-03-24 04:41:43 +00:00
Chris Lattner
4318a3d0e9 cleanup the cfg after lsr 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20410 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-03-02 21:56:00 +00:00
Chris Lattner
0c7490617a Add a temporary option for llc-beta: -enable-lsr-for-ppc, which turns on 
Loop Strength Reduction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20399 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-03-02 06:19:22 +00:00
Chris Lattner
3ea78c4276 Use the target triple to pick this target. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18830 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-12-12 17:40:28 +00:00
Chris Lattner
9d0087e043 The LLVM bool type shall have 1 byte alignment on PPC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18311 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-11-28 21:16:45 +00:00
Chris Lattner
2a0c0dff0b The JIT works enough 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18228 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-11-25 04:14:54 +00:00
Chris Lattner
05ad23711e Remove this method. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18159 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-11-23 18:47:42 +00:00
Nate Begeman
dd30751654 Don't return value from void function. This is only temporary anyway while 
the JIT is made to work!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18155 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-11-23 10:04:49 +00:00
Chris Lattner
c9a6b1f4f6 Be really paranoid about not breaking stuff yet 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18152 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-11-23 06:56:18 +00:00
Chris Lattner
e4fce6f19c Move JITInfo from PPCTM to PPC32TM 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18140 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-11-23 05:56:40 +00:00
Chris Lattner
1deb74d7ee Remove this method, it's not clear how it could be implemented indep of 32 or 64-bit mode 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18038 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-11-20 04:17:17 +00:00
Chris Lattner
097714b319 Disable the JIT until it can sorta kinda work. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17230 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-10-25 20:53:41 +00:00
Chris Lattner
cbb9812d0d bling bling! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16873 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-10-10 16:26:13 +00:00
Nate Begeman
ed42853be1 All PPC instructions are now auto-printed 
32 and 64 bit AsmWriters unified
Darwin and AIX specific features of AsmWriter split out


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16163 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-09-04 05:00:00 +00:00
Reid Spencer
551ccae044 Changes For Bug 352 
Move include/Config and include/Support into include/llvm/Config,
include/llvm/ADT and include/llvm/Support. From here on out, all LLVM
public header files must be under include/llvm/.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16137 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-09-01 22:55:40 +00:00
Chris Lattner
f908888553 Do not register ppc64 yet, as it breaks the SparcV9 backend 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15955 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-20 18:09:18 +00:00
Misha Brukman
983e92dc0d LR needs to be saved at 16-byte offset on a 64-bit arch 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15929 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-19 21:36:14 +00:00
Misha Brukman
66aa3e0e8b No need for an `is64bit' flag 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15857 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-17 05:06:47 +00:00
Nate Begeman
ca068e861b Replace PowerPCPEI.cpp with target independant PrologEpilogInserter 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15746 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-14 22:16:36 +00:00
Misha Brukman
f5f70685b6 Disable PPC64 backend by default because LLC cannot choose automatically between 
SparcV9 and PowerPC64 without target triples, since they are both 64-bit
big-endian targets.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15688 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-12 17:16:43 +00:00
Misha Brukman
1d3527edbf * Move AIX into the llvm namespace to be accessed from RegisterInfo 
* Mark InstrInfo with 32 vs. 64 bit flag
* Enable the 64-bit isel and asm printer


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15672 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-11 23:47:08 +00:00
Misha Brukman
9582822341 Hyphenate ##-bit and remove first-person from comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15663 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-11 13:35:44 +00:00
Nate Begeman
7a4fe9be7e Clean up 32/64bit and Darwin/AIX split. Next steps: 64 bit ISel, AIX asm printer. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15662 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-11 07:40:04 +00:00
Misha Brukman
0145881cb9 Breaking up the PowerPC target into 32- and 64-bit subparts, Part III: the rest. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15636 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-11 00:11:25 +00:00
Misha Brukman
7103fba019 CodePrinter -> AsmPrinter 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15599 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-09 22:27:45 +00:00
Chris Lattner
3ea934668b Changes commited for Nate Begeman: 
Use a PowerPC specific prolog epilog inserter to control where spilled
callee save regs are placed on the stack.
Get rid of implicit return address stack slot, save return address reg
(LR) in appropriate slot
Improve code generated for functions that don't have calls or access
globals


Note from Chris: PowerPCPEI will eventually be eliminated, once the
functionality is merged into CodeGen/PrologEpilogInserter.cpp


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15536 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-06 06:58:50 +00:00
Misha Brukman
bd2c870539 Run the branch selection pass right before the asm printer. 
Patch by Nate Begeman.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15285 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-07-27 18:39:34 +00:00
Misha Brukman
9accb24c89 Bool alignment on MacOSX/PowerPC is 4 bytes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15122 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-07-23 01:11:46 +00:00
Misha Brukman
cd2273f4a7 Shorts are aligned to 2 bytes, bools to 1 byte (in structs). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15048 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-07-20 20:59:57 +00:00
Misha Brukman
5c4544160f Double alignment in structs is 4 bytes, not 8. Patch by Nate Begeman. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15034 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-07-20 15:43:25 +00:00
Misha Brukman
a57b76fece We don't really need to #include IPO.h into this file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14911 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-07-17 18:37:46 +00:00
Misha Brukman
6f14ad1ca0 Define double alignment as 8 bytes now that assert(DoubleAlignment == PointerSize) 
has been eliminated


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14891 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-07-16 19:32:12 +00:00
Chris Lattner
017fdcb76d Revert stuff that I didn't mean to checkin 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14844 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-07-15 02:33:38 +00:00
Chris Lattner
76e2df2645 Patches towards fixing PR341 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14841 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-07-15 02:14:30 +00:00
Misha Brukman
01eca8d2c2 Implement getModuleMatchQuality and getJITMatchQuality() for PowerPC 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14780 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-07-12 23:36:12 +00:00
Chris Lattner
68905bb6fc Delete the allocate*TargetMachine function, which is now dead. 
The shared command line options are now in a header that makes sense.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14757 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-07-11 04:17:58 +00:00
Chris Lattner
71d24aab2d Make these format a bit nicer 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14747 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-07-11 03:27:42 +00:00