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5 Commits

Author SHA1 Message Date
Preston Gurd
7813a2fe9d Forgot to add a break statement. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191715 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-30 23:51:22 +00:00
Preston Gurd
2967a80412 The X86FixupLEAs pass for Intel Atom must not call convertToThreeAddress 
on ADD16rr opcodes, if src1 != src, since that would cause 
convertToThreeAddress to try to create a virtual register. This is not
permitted after register allocation, which is when the X86FixupLEAs pass
runs.

This patch fixes PR16785.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191711 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-30 23:18:42 +00:00
Bill Wendling
a5e5ba611f Don't cache the instruction and register info from the TargetMachine, because 
the internals of TargetMachine could change.

No functionality change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183571 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 21:00:34 +00:00
Preston Gurd
7f8300b8f3 Make function documentation conform to llvm standards. 
Expunge all remaining traces and use of live variable information.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180577 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-25 21:31:33 +00:00
Preston Gurd
d6ac8e9a03 This patch adds the X86FixupLEAs pass, which will reduce instruction 
latency for certain models of the Intel Atom family, by converting
instructions into their equivalent LEA instructions, when it is both
useful and possible to do so.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180573 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-25 20:29:37 +00:00