state was being executed too lazily, and the LLVM
assembly syntax for the disassembler was not being
written into the proper disassembler state variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100830 91177308-0d34-0410-b5e6-96231b3b80d8
I also added a rule to the ARM target's Makefile to
build the ARM-specific instruction information table
for the enhanced disassembler.
I will add the test harness for all this stuff in
a separate commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100735 91177308-0d34-0410-b5e6-96231b3b80d8
argument that had to be between 0 and 7 to have any value,
firing an assert later in the AsmPrinter. Now, the
disassembler rejects instructions with out-of-range values
for that immediate.
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return an error status in all failure cases, printing
messages to debugs() only when debugging is enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100229 91177308-0d34-0410-b5e6-96231b3b80d8
on Mac OS X to use @rpath rather than an absolute
path. Also allowed the version to be set using an
environment variable.
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whose opcodes extend into the ModR/M field using the
Form field of the instruction rather than by special
casing each instruction. Commented out the special
casing of VMCALL, which is the first instruction to use
this special form. While I was in the neighborhood,
added a few comments for people modifying the Intel
disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96043 91177308-0d34-0410-b5e6-96231b3b80d8
operand into the CodeGenInstruction's list of operands,
which is useful for EDEmitter. (Still working on PR6219)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95759 91177308-0d34-0410-b5e6-96231b3b80d8
implementation. Also changed the constructor
so that it does not require a Record, making it
usable by the EDEmitter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95715 91177308-0d34-0410-b5e6-96231b3b80d8
out of the AsmWriterEmitter. This patch does the physical
code movement, but leaves the implementation unchanged. I'll
make any changes necessary to generalize the code in a
separate patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95697 91177308-0d34-0410-b5e6-96231b3b80d8
for register tokens. Before, if it encountered
'%al,' it would report 'al,' as the token. Now it
correctly reports '%al'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95594 91177308-0d34-0410-b5e6-96231b3b80d8
disassembly library that provide access to
instruction information, and fixed ambiguous
wording in the comments for the header.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95274 91177308-0d34-0410-b5e6-96231b3b80d8
yesterday. This eliminates possible confusion
about what exactly in this directory; the name
is still short, though.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95118 91177308-0d34-0410-b5e6-96231b3b80d8
implementation. Also made sure that the register maps
were created during disassembler initialization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95051 91177308-0d34-0410-b5e6-96231b3b80d8
merely stubs out the blocks-based disassembly functions
if the library wasn't built with blocks, which allows a
constant .exports file and also properly deals with
situations in which the compiler used to build a client
is different from the compiler used to build the library.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95034 91177308-0d34-0410-b5e6-96231b3b80d8
fleshed out the .exports file. I still have to fix several
details of operand parsing, but the basic functionality is
there and usable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94974 91177308-0d34-0410-b5e6-96231b3b80d8
to the TargetAsmLexer class so that clients can
actually use the TargetAsmLexer they get from a
Target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94940 91177308-0d34-0410-b5e6-96231b3b80d8
library as a static and a shared library. Added dependencies
so the target-specific enhanced disassembly info tables are
built before the library.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94780 91177308-0d34-0410-b5e6-96231b3b80d8
TargetAsmLexer. Dialect-specific lexing code will
be placed in the functions LexTokenATT() and
LexTokenIntel().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94456 91177308-0d34-0410-b5e6-96231b3b80d8
be static. Also made it possible for clients to get it
and no other functions from ...GenAsmMatcher.inc by
defining REGISTERS_ONLY before including GenAsmMatcher.inc.
This sets the stage for target-specific lexers that can
identify registers and return AsmToken::Register as
appropriate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94266 91177308-0d34-0410-b5e6-96231b3b80d8
exactly like an MCAsmLexer. (The difference is that the
TargetAsmLexer knows how to handle target-specific stuff
like registers, whereas the MCAsmLexer is fully generic.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94237 91177308-0d34-0410-b5e6-96231b3b80d8
rather than passing them off to the AsmLexer to handle.
This means the AsmLexer no longer requires a SourceMgr
to do error handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94047 91177308-0d34-0410-b5e6-96231b3b80d8
the two token accessor functions are declared consistently.
Modified the clients of MCAsmParser to reflect this change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93916 91177308-0d34-0410-b5e6-96231b3b80d8
of include directives to occur within the parser itself.
This will break the lexer's dependency on a SourceMgr as
input.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93899 91177308-0d34-0410-b5e6-96231b3b80d8
Made LEA memory operands emit only 4 MCInst operands.
Made the scale operand equal 1 for instructions that have no
SIB byte.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91919 91177308-0d34-0410-b5e6-96231b3b80d8
incarnations), integrated into the MC framework.
The disassembler is table-driven, using a custom TableGen backend to
generate hierarchical tables optimized for fast decode. The disassembler
consumes MemoryObjects and produces arrays of MCInsts, adhering to the
abstract base class MCDisassembler (llvm/MC/MCDisassembler.h).
The disassembler is documented in detail in
- lib/Target/X86/Disassembler/X86Disassembler.cpp (disassembler runtime)
- utils/TableGen/DisassemblerEmitter.cpp (table emitter)
You can test the disassembler by running llvm-mc -disassemble for i386
or x86_64 targets. Please let me know if you encounter any problems
with it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91749 91177308-0d34-0410-b5e6-96231b3b80d8
with -disassemble, llvm-mc now accepts lines of the
form
0x00 0x00
and passes the resulting bytes to the disassembler for
the chosen (or default) target, printing the result.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91579 91177308-0d34-0410-b5e6-96231b3b80d8
Also fixed the corresponding testcase, and the PALIGNR
intrinsic (tested for correctness with llvm-gcc).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89491 91177308-0d34-0410-b5e6-96231b3b80d8
the Intel instruction tables.
The patterns will stay blank because ADD reg, reg
is faster, but having the encoding available is
useful for the disassembler.
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All of these do not have patterns (they're for the
disassembler).
Many of the floating-point instructions will probably
be rolled into definitions that have patterns, and may
eventually be superseded by mdefs. So I put them
together and left a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81979 91177308-0d34-0410-b5e6-96231b3b80d8
Intel tables, where the source operand is
specified by the R/M field and the destination
operand by the Reg field.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81914 91177308-0d34-0410-b5e6-96231b3b80d8
to the Intel register table.
Added 16- and 64-bit MOVs to and from the segment
registers to the Intel instruction tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81895 91177308-0d34-0410-b5e6-96231b3b80d8
all disassemblers.
Modified the MemoryObject to support 64-bit address
spaces, regardless of the LLVM process's address
width.
Modified the Target class to allow extraction of a
MCDisassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81392 91177308-0d34-0410-b5e6-96231b3b80d8
instruction tables to support segmented addressing (and other objects
of obscure type).
Modified the X86 assembly printers to handle these new operand types.
Added JMP and CALL instructions that use segmented addresses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80857 91177308-0d34-0410-b5e6-96231b3b80d8
INT i8. These instructions are only for interpretation by disassemblers, not
for emission, so they do not as yet have patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78630 91177308-0d34-0410-b5e6-96231b3b80d8
I'm returning the number of bytes actually copied so that the client has some
warning when it reads past the end of the buffer.
I'm keeping the distinction between getByte() and getBytes() for now for
subclasses that use functions like ptrace() on Linux and only have a restricted
interface. This makes their implementation easier, and subclasses can always
write a one-line implementation of readByte() that uses their custom
readBytes().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77225 91177308-0d34-0410-b5e6-96231b3b80d8
Necessary for cases in which the memory is in another process, in a
file, or on a remote machine.
The primary use for this is the llvm-mc disassemblers, so that they
can be targeted at arbitrary objects, not just in-process memory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77023 91177308-0d34-0410-b5e6-96231b3b80d8
Sean Callanan