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88 Commits

Author SHA1 Message Date
Jozef Kolek
c623d0af3d [mips][microMIPS] Implement CACHE, PREF, SSNOP, EHB and PAUSE instructions 
Differential Revision: http://reviews.llvm.org/D5204


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224785 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-23 19:55:34 +00:00
Jozef Kolek
e5fa612e9e [mips][microMIPS] Implement LWSP and SWSP instructions 
Differential Revision: http://reviews.llvm.org/D6416


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224771 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-23 16:16:33 +00:00
Zoran Jovanovic
78f6aad800 [mips][microMIPS] Implement SWP and LWP instructions 
Differential Revision: http://reviews.llvm.org/D5667


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224338 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-16 14:59:10 +00:00
Jozef Kolek
c3692e5c67 [mips][microMIPS] Implement CodeGen support for LI16 instruction. 
Differential Revision: http://reviews.llvm.org/D5840


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224017 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-11 13:56:23 +00:00
Vladimir Medic
462763dc0b The andi16, addiusp and jraddiusp micromips instructions were missing dedicated decoder methods in MipsDisassembler.cpp to properly decode immediate operands. These methods are added together with corresponding tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223006 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-01 11:12:04 +00:00
Jozef Kolek
b087448a5f [mips][microMIPS] Implement NOP aliases 
This patch implements microMIPS 16-bit (MOVE16 $0, $0) and
32-bit (SLL $0, $0, 0) NOP aliases.

http://reviews.llvm.org/D6440


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222953 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-29 13:29:24 +00:00
Zoran Jovanovic
7dc6143a82 [mips][microMIPS] Implement SWM16 and LWM16 instructions 
Differential Revision: http://reviews.llvm.org/D5579


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222901 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-27 18:28:59 +00:00
Jozef Kolek
13fbabb7c8 [mips][microMIPS] Implement BREAK16 and SDBBP16 instructions 
Patch by Radovan Obradovic.

Differential Revision: http://reviews.llvm.org/D5048


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222900 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-27 18:18:42 +00:00
Jozef Kolek
2b8e58cc82 [mips][microMIPS] Implement disassembler support for 16-bit instructions LI16, ADDIUR1SP, ADDIUR2 and ADDIUS5 
Differential Revision: http://reviews.llvm.org/D6419


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222887 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-27 14:41:44 +00:00
Jozef Kolek
832e2301cd [mips][microMIPS] Implement disassembler support for 16-bit instructions LBU16, LHU16, LW16, SB16, SH16 and SW16 
Differential Revision: http://reviews.llvm.org/D6405


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222847 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-26 18:56:38 +00:00
Jozef Kolek
c19526770e [mips][microMIPS] Fix JRADDIUSP instruction 
Fix JRADDIUSP instruction, remove delay slot flag because this instruction
doesn't have delay slot.

Differential Revision: http://reviews.llvm.org/D6365


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222658 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-24 16:14:10 +00:00
Jozef Kolek
b955bed064 [mips][microMIPS] Implement LBU16, LHU16, LW16, SB16, SH16 and SW16 instructions 
Differential Revision: http://reviews.llvm.org/D5122


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222653 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-24 14:39:13 +00:00
Zoran Jovanovic
d67cd80220 [mips][micromips] Implement SWM32 and LWM32 instructions 
Differential Revision: http://reviews.llvm.org/D5519


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222367 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-19 16:44:02 +00:00
Jozef Kolek
e4e84b22fe [mips][microMIPS] Implement CodeGen support for 16-bit instruction ADDIUR2. 
Differential Revision: http://reviews.llvm.org/D5800


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222352 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-19 13:23:58 +00:00
Jozef Kolek
5c6c7e3295 [mips][microMIPS] Implement CodeGen support for ADDIUS5 instruction. 
Differential Revision: http://reviews.llvm.org/D5799


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222351 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-19 13:11:09 +00:00
Jozef Kolek
43ae00e4e0 [mips][microMIPS] Implement LWXS instruction. 
Differential Revision: http://reviews.llvm.org/D5407


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222348 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-19 11:39:12 +00:00
Jozef Kolek
baf97d8987 [mips][microMIPS] Implement SDBBP and RDHWR instructions. 
Differential Revision: http://reviews.llvm.org/D5240


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222347 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-19 11:25:50 +00:00
Zoran Jovanovic
cb5fadfe6a [mips][micromips] Add predicate 'InMicroMips' at CodeGen patterns for microMIPS instructions 
Differential Revision: http://reviews.llvm.org/D6198


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221780 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-12 13:30:10 +00:00
Zoran Jovanovic
cd2d40cef6 ps][microMIPS] Implement CodeGen support for ANDI16 instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221371 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-05 17:43:00 +00:00
Zoran Jovanovic
a1925e6d5d ps][microMIPS] Implement CodeGen support for SLL16 and SRL16 instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221369 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-05 17:38:31 +00:00
Zoran Jovanovic
8dad1e1e8e [mips][microMIPS] Implement ANDI16 instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221367 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-05 17:31:00 +00:00
Zoran Jovanovic
e9b9ca452f Reverted revisions 221351, 221352 and 221353. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221354 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-05 16:19:59 +00:00
Zoran Jovanovic
e7ec22de06 [mips][microMIPS] Implement CodeGen support for ANDI16 instruction 
Differential Revision: http://reviews.llvm.org/D5797


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221353 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-05 15:54:05 +00:00
Zoran Jovanovic
8cfd4909f0 [mips][microMIPS] Implement CodeGen support for SLL16 and SRL16 instructions 
Differential Revision: http://reviews.llvm.org/D5933


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221352 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-05 15:46:53 +00:00
Zoran Jovanovic
7c63a6331f [mips][microMIPS] Implement ANDI16 instruction 
Differential Revision: http://reviews.llvm.org/D5163


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221351 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-05 15:39:41 +00:00
Zoran Jovanovic
71832e7ed9 [mips][microMIPS] Implement ADDIUR1SP instruction 
Differential Revision: http://reviews.llvm.org/D5153


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220477 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-23 11:13:59 +00:00
Zoran Jovanovic
fd515137bc ps][microMIPS] Implement ADDIUR2 instruction 
Differential Revision: http://reviews.llvm.org/D5151


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220476 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-23 11:06:34 +00:00
Zoran Jovanovic
f58c95aac0 ps][microMIPS] Implement LI16 instruction 
Differential Revision: http://reviews.llvm.org/D5149


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220475 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-23 10:59:24 +00:00
Zoran Jovanovic
558236adf0 [mips][microMIPS] Implement CodeGen support for SLL16 and SRL16 instructions 
Differential Revision: http://reviews.llvm.org/D5774


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220474 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-23 10:42:01 +00:00
Zoran Jovanovic
59e16813d2 [mips][microMIPS] Implement ADDU16 and SUBU16 instructions 
Differential Revision: http://reviews.llvm.org/D5118


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220276 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-21 08:44:58 +00:00
Zoran Jovanovic
a245b68293 [mips][microMIPS] Implement AND16, NOT16, OR16 and XOR16 instructions 
Differential Revision: http://reviews.llvm.org/D5117


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220275 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-21 08:32:40 +00:00
Zoran Jovanovic
0bf4807a90 [mips][microMIPS] Implement ADDIUSP instruction 
Differential Revision: http://reviews.llvm.org/D5084


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219500 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-10 14:37:30 +00:00
Zoran Jovanovic
24335e60c7 [mips][microMIPS] Implement JR16 instruction 
Differential Revision: http://reviews.llvm.org/D5062


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219498 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-10 14:02:44 +00:00
Zoran Jovanovic
e2db3024be [mips][microMIPS] Implement ADDIUS5 instruction 
Differential Revision: http://reviews.llvm.org/D5049


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219495 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-10 13:45:34 +00:00
Zoran Jovanovic
28b2826538 ps][microMIPS] Implement JRC instruction 
Differential Revision: http://reviews.llvm.org/D5045


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219494 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-10 13:31:18 +00:00
Zoran Jovanovic
b581230077 [mips][microMIPS] Implement JALRS16 instruction 
Differential Revision: http://reviews.llvm.org/D5027


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219493 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-10 13:22:28 +00:00
Zoran Jovanovic
614d8681e0 [mips][microMIPS] Implement JRADDIUSP instruction 
Differential Revision: http://reviews.llvm.org/D5046


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217681 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-09-12 14:29:54 +00:00
Zoran Jovanovic
7fd9d5636a [mips][microMIPS] Implement BGEZALS and BLTZALS instructions 
Differential Revision: http://reviews.llvm.org/D5004


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217678 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-09-12 13:51:58 +00:00
Zoran Jovanovic
cf6da9bed3 [mips][microMIPS] Implement JALS and JALRS instructions. 
Differential Revision: http://reviews.llvm.org/D5003


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217676 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-09-12 13:43:41 +00:00
Zoran Jovanovic
75449bc4d7 [mips][microMIPS] Implement TLBP, TLBR, TLBWI and TLBWR instructions 
Differential Revision: http://reviews.llvm.org/D5211


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217675 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-09-12 13:33:33 +00:00
Zoran Jovanovic
cdcacd7568 [mips][microMIPS] MicroMIPS Compact Branch Instructions BEQZC and BNEZC 
Differential Revision: http://reviews.llvm.org/D3545


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215636 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-08-14 12:09:10 +00:00
Daniel Sanders
7c2ef822f7 [mips][mips64r6] Use JALR for returns instead of JR (which is not available on MIPS32r6/MIPS64r6) 
Summary:
RET, and RET_MM have been replaced by a pseudo named PseudoReturn.
In addition a version with a 64-bit GPR named PseudoReturn64 has been
added.

Instruction selection for a return matches RetRA, which is expanded post
register allocation to PseudoReturn/PseudoReturn64. During MipsAsmPrinter,
this PseudoReturn/PseudoReturn64 are emitted as:
- (JALR64 $zero, $rs) on MIPS64r6
- (JALR $zero, $rs) on MIPS32r6
- (JR_MM $rs) on microMIPS
- (JR $rs) otherwise

On MIPS32r6/MIPS64r6, 'jr $rs' is an alias for 'jalr $zero, $rs'. To aid
development and review (specifically, to ensure all cases of jr are
updated), these aliases are temporarily named 'r6.jr' instead of 'jr'.
A follow up patch will change them back to the correct mnemonic.

Added (JALR $zero, $rs) to MipsNaClELFStreamer's definition of an indirect
jump, and removed it from its definition of a call.
Note: I haven't accounted for MIPS64 in MipsNaClELFStreamer since it's
doesn't appear to account for any MIPS64-specifics.

The return instruction created as part of eh_return expansion is now expanded
using expandRetRA() so we use the right return instruction on MIPS32r6/MIPS64r6
('jalr $zero, $rs').

Also, fixed a misuse of isABI_N64() to detect 64-bit wide registers in
expandEhReturn().

Reviewers: jkolek, vmedic, mseaborn, zoran.jovanovic, dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D4268


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212604 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-07-09 10:16:07 +00:00
Daniel Sanders
0e0f907356 [mips] Marked up instructions added in MIPS32r2 and tested that IAS for -mcpu=mips(2|32) does not accept them 
Summary:
This required a new instruction group representing the 32-bit subset of
MIPS-3 that was available in MIPS32R2.

To limit the number of tests required, only one 32-bit and one 64-bit ISA
prior to MIPS32/MIPS64 are tested.

rdhwr has been deliberately left without an ISA annotation for now. This is
because the assembler and CodeGen disagree on when the instruction is
available. Strictly speaking, it is only available in MIPS32r2 and
MIPS64r2. However, it is emulated by a kernel trap on earlier ISA's and is
necessary for TLS so CodeGen should emit it on older ISA's too.

Depends on D3696

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3697

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208690 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-13 11:45:36 +00:00
Daniel Sanders
b396af3752 [mips] Fold FeatureBitCount into FeatureMips32 and FeatureMips64 
Summary:
DCL[ZO] are now correctly marked as being MIPS64 instructions. This has no
effect on the CodeGen tests since expansion of i64 prevented their use
anyway.

The check for MIPS16 to prevent the use of CLZ no longer prevents DCLZ as
well. This is not a functional change since DCLZ is still prohibited by
being a MIPS64 instruction (MIPS16 is only compatible with MIPS32).

No functional change

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3694

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208544 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-12 12:41:59 +00:00
Daniel Sanders
ea27d2f50b [mips] Fold FeatureSEInReg into FeatureMips32r2 
Summary: No functional change

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3693

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208543 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-12 12:28:15 +00:00
Daniel Sanders
d46b2e219d [mips] Fold FeatureSwap into FeatureMips32r2 and FeatureMips64r2 
Summary:
dsbh and dshd are not available on Mips32r2. No codegen test changes
required since expansion of i64 prevented the use of these instructions
anyway.

Depends on D3690

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3692

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208542 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-12 12:15:41 +00:00
Daniel Sanders
d41a985f33 [mips] Add PredicateControl to InstAlias's 
Summary:
No functional change

Depends on D3649

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3672

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208334 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-08 16:12:31 +00:00
Zoran Jovanovic
4d24300247 Implementation of 16-bit microMIPS instructions MFHI and MFLO. 
Differential Revision: http://llvm-reviews.chandlerc.com/D3141


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205532 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-03 12:47:34 +00:00
Zoran Jovanovic
077aa54e4e Fixed issue with microMIPS JAL instruction. 
Differential Revision: http://llvm-reviews.chandlerc.com/D3200


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205185 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-31 14:00:10 +00:00
Zoran Jovanovic
37fb9b9591 Provide an operand for microMIPS wait instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204329 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-20 10:41:37 +00:00