6 Commits

Author	SHA1	Message	Date
Mihai Popa	16ad92ad3c	This patch adds support for FPINST/FPINST2 as operands to vmsr/vmrs. These are optional registers that may be supported some ARM implementations to aid with resolution of floating point exceptions. The manual pages for vmsr and vmrs do not detail their use. Encodings and other information can be found in ARM Architecture Reference Manual section F, chapter 6, paragraph 3. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183733 91177308-0d34-0410-b5e6-96231b3b80d8	2013-06-11 09:39:51 +00:00
Tim Northover	242c9f4615	ARM: add fstmx and fldmx instructions for assembly ... These instructions are deprecated oddities, but we still need to be able to disassemble (and reassemble) them if and when they're encountered. Patch by Amaury de la Vieuville. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183011 91177308-0d34-0410-b5e6-96231b3b80d8	2013-05-31 15:55:51 +00:00
Silviu Baranga	b422d0b65e	Fixed disassembler for vstm/vldm ARM VFP instructions. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156077 91177308-0d34-0410-b5e6-96231b3b80d8	2012-05-03 16:38:40 +00:00
Evan Cheng	cac31de146	Specify cpu to unbreak tests. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155604 91177308-0d34-0410-b5e6-96231b3b80d8	2012-04-26 01:38:10 +00:00
Jim Grosbach	ffc658b056	ARM VLDR/VSTR instructions don't need a size suffix. ... Canonicallize on the non-suffixed form, but continue to accept assembly that has any correctly sized type suffix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144583 91177308-0d34-0410-b5e6-96231b3b80d8	2011-11-14 23:03:21 +00:00
Owen Anderson	c4bda5633a	Add some more comprehensive VFP decoding tests. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137657 91177308-0d34-0410-b5e6-96231b3b80d8	2011-08-15 21:29:01 +00:00