901b85888c
Include cstdio in a few place that depended on getting it transitively through StringExtras.h
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153328 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-23 11:35:30 +00:00
e68e77569f
Move ftostr into its last user (cppbackend) and simplify it a bit.
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New code should use raw_ostream.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153326 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-23 11:26:29 +00:00
a443e5b1f1
Remove the C backend.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153307 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-23 05:50:46 +00:00
6fe310e155
Added soft fail checks for the disassembler when decoding some corner cases of the STRD, STRH, LDRD, LDRH, LDRSH and LDRSB instructions on ARM.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153252 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-22 14:14:49 +00:00
b7c2ed6664
Added soft fail cases for the disassembler when decoding LDRSBT, LDRHT or LDRSHT instruction on ARM
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153251 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-22 13:24:43 +00:00
a0c48eb8f6
Added soft fail cases for the disassembler when decoding MUL instructions on ARM.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153250 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-22 13:14:39 +00:00
63bd926a41
Remove some unnecessary forward declarations.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153245 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-22 06:52:14 +00:00
f2f6182f6a
PPC::DBG_VALUE must use Reg+Imm frame-index elimination even for large offsets. Fixes PR12203.
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I don't have a small test case yet, but I'll try to construct one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153240 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-22 05:28:19 +00:00
f0586f08df
Fix ARM disassembly of VST1 and VST2 instructions with writeback. And add test
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case for all opcodes handed by DecodeVSTInstruction() in ARMDisassembler.cpp .
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153218 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-21 20:54:32 +00:00
d9e85ef08b
Put Is64BitMemOperand into !defined(NDEBUG) for now.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153185 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-21 14:09:26 +00:00
47817f30f2
Use a signed value for this enum to avoid spuriuos warnings from gcc.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153184 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-21 13:48:11 +00:00
4fd3d29275
Fix generation of the address size override prefix. Add assertions for
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the invalid cases. At least 16bit operand in 64bit mode is currently not
rejected in the parser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153166 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-21 05:48:07 +00:00
9be7c94ccd
Add typecast to silence -Wswitch warning introduced by r153153.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153155 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-21 02:28:53 +00:00
3d092dbb91
Spacing fixes and using 'unsigned' instead of 'int' to index to select shuffle elements for consistency with other shuffle code in X86 backend.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153154 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-21 02:14:01 +00:00
fb54afbcb8
Incremental big endian patch by Jack Carter.
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These changes allow us to compile big endian from the command line for 32 bit
Mips targets. This patch will result in code and data actually being produced
in the correct endianess.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153153 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-21 00:52:01 +00:00
1b1fdc0599
[avx] Add patterns for combining vextractf128 + vmovaps/vmovups/vmobdqu to
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vextractf128 with 128-bit mem dest.
Combines
vextractf128 $0, %ymm0, %xmm0
vmovaps %xmm0, (%rdi)
to
vextractf128 $0, %ymm0, (%rdi)
rdar://11082570
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153139 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20 21:43:40 +00:00
03a1852538
Change conditional instructions definitions, e.g. ANDCC, ARMPseudoExpand and t2PseudoExpand.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153135 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20 21:28:05 +00:00
98a27acc6b
remove unused variable
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153116 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20 19:52:05 +00:00
a3bfdf536e
[avx] Add the AddedComplexity to the VINSERTI128 avx2 patterns to give
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precedence over the VINSERTF128 avx1 patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153114 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20 19:45:07 +00:00
aaa1e2f820
Require a base pointer for stack realignment when SP may vary dynamically.
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ARMBaseRegisterInfo::canRealignStack was checking for variable-sized objects
but not for stack adjustments around calls. Use hasReservedCallFrame() to
check for both. The hasBasePointer function was already correctly checking
both conditions, so the effect of this was that a base pointer would be used
without checking whether the base pointer register could be reserved. I don't
have a small testcase for this.
<rdar://problem/11075906>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153110 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20 19:28:25 +00:00
055a8127c9
Remove some redundant checks.
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ARMFrameLowering::hasReservedCallFrame is already checking for variable
sized objects, so there's no point in checking it twice.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153109 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20 19:28:22 +00:00
666da1611a
Whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153105 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20 18:38:33 +00:00
36a273a76c
[avx] Move the vextractf128 patterns closer to the vextractf128 def. Remove
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whitespace from test case. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153103 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20 18:24:55 +00:00
9f2e160f7a
Fix assembling ARM vst2 instructions with double-spaced registers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153099 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20 17:41:51 +00:00
07cdd80ccc
ARM non-scattered MachO relocations for movw/movt.
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Needed when building -mdynamic-no-pic code.
rdar://10459256
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153097 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20 17:25:45 +00:00
33e528d44d
[avx] Adjust the VINSERTF128rm pattern to allow for unaligned loads.
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This results in things such as
vmovups 16(%rdi), %xmm0
vinsertf128 $1, %xmm0, %ymm0, %ymm0
to be combined to
vinsertf128 $1, 16(%rdi), %ymm0, %ymm0
rdar://11076953
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153092 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20 17:08:51 +00:00
5c062ad926
The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153089 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20 15:54:56 +00:00
db9ca59759
Test Commit - add a newline
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153083 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20 10:50:35 +00:00
89f4e6639d
Remove code that prevented lowering shuffles if they are used by load and themselves used by a extract_vector_elt. This was done to allow the DAG combiner to collapse to a single element load. Unfortunately, sometimes the extract_vector_elt would disappear before DAG combine could do the transformation leaving a vector_shuffle that isel couldn't handle. New code lets the shuffle be converted to a target specific node, but then adds a combine routine that can convert target specific nodes back to vector_shuffles if the folding criteria are met.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153080 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20 07:17:59 +00:00
a1ffc681ed
Factor out target shuffle mask decoding from getShuffleScalarElt and use a SmallVector of int instead of unsigned for shuffle mask in decode functions. Preparation for another change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153079 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20 06:42:26 +00:00
e59b0e777d
fix a build failure with libc++
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153063 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-19 23:31:01 +00:00
fa1f74470a
ARM branch relaxation for unconditional t1 branches.
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rdar://11059157
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153055 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-19 21:32:32 +00:00
ceee984302
ARM assembly, accept optional '#' on lane index number.
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rdar://11057160
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153053 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-19 20:39:53 +00:00
2d7ea04e28
Perform mul combine when multiplying wiht negative constants.
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Patch by Weiming Zhao!
This fixes PR12212
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153049 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-19 19:19:50 +00:00
3e99b715d1
This patch adds X86 instruction itineraries for non-pseudo opcodes in
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X86InstrCompiler.td.
It also adds –mcpu-generic to the legalize-shift-64.ll test so the test
will pass if run on an Intel Atom CPU, which would otherwise
produce an instruction schedule which differs from that which the test expects.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153033 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-19 14:10:12 +00:00
8118c94a55
Add a note for -ffast-math optimization of vector norm.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153031 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-19 00:43:34 +00:00
97327dc6ef
isCommutedMOVLMask should only look at 128-bit vectors to match isMOVLMask.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153027 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-18 22:50:10 +00:00
79aa3417eb
Reorder includes in Target backends to following coding standards. Remove some superfluous forward declarations.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152997 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-17 18:46:09 +00:00
70de1e442d
Fix some copy and paste remnants of Cell and SPU in Hexagon files.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152981 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-17 09:39:20 +00:00
8aea2dd964
Fix typo in file header.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152980 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-17 09:28:37 +00:00
1e0c9ab0d1
Pass TargetOptions to HexagonTargetMachine constructor by reference to match other targets and the base class.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152979 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-17 09:24:09 +00:00
c1f6f42049
Reorder includes to match coding standards. Fix an issue or two exposed by that.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152978 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-17 07:33:42 +00:00
5aeff3171c
Check if we can handle the arguments of a call (and therefore the call) in
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fast-isel before emitting code. If the program bails after code was emitted,
then it could lead to the stack being adjusted more than once (two
CALLSEQ_BEGINs emitted) but being adjuste back only once after the call. This
leads to general badness and gnashing of teeth.
<rdar://problem/11050630>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152959 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-16 23:11:07 +00:00
11d5dc3d50
ARM fix silly typo in optional operand alias.
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rdar://11065671
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152954 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-16 22:18:29 +00:00
66cba302f0
ARM divided syntax fmrx/fmxr mnemonics.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152946 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-16 21:06:13 +00:00
be7cf2b377
ARM ldm/stm register lists can be out of order.
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It's not a good style idea, as the registers will be laid down in memory in
numerical order, not the order they're in the list, but it's legal. vldm/vstm
are stricter.
rdar://11064740
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152943 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-16 20:48:38 +00:00
213d2e7dc3
ARM optional operand on MRC/MCR assembly instructions.
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rdar://11058464
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152883 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-16 00:45:58 +00:00
9426ac7b57
ARM vmrs system registers mvfr0 and mvfr1 handling.
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rdar://11058464
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152881 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-16 00:27:18 +00:00
89eaa6f554
Remove inadvertant commit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152870 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-15 23:00:30 +00:00
0ac754f6f4
[fast-isel] Address Eli's comments for r152847. Specifically, add a test case
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and still allow immediate encoding, just not with cmn.
rdar://11038907
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152869 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-15 22:54:20 +00:00
