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14935 Commits

Author SHA1 Message Date
Dan Gohman
9559e3b99a Silence compiler warnings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106360 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-19 00:02:06 +00:00
Bruno Cardoso Lopes
c82f199892 more refactoring! yay! big win over the intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106359 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-19 00:00:22 +00:00
Eric Christopher
96ab7f494d Remove isTwoAddress from here too. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106358 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 23:56:07 +00:00
Bruno Cardoso Lopes
ccf30bd984 Fix typo, SSE1 should be used by XS, not SSE2 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106357 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 23:53:27 +00:00
Eric Christopher
f6bc0b9d4b Remove isTwoAddress from 64-bit files. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106356 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 23:51:21 +00:00
Evan Cheng
96c3da6436 Move ARM if-conversion before post-ra scheduling. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106355 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 23:32:07 +00:00
Dan Gohman
db4971259c Teach regular and fast isel to set dead flags on unused implicit defs 
on calls and similar instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106353 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 23:28:01 +00:00
Bruno Cardoso Lopes
8af5ed9e15 Apply some refactor to packed instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106349 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 23:13:35 +00:00
Evan Cheng
3ee608c5aa Update cmake list. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106348 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 23:12:10 +00:00
Evan Cheng
886459456c Thumb2 hazard recognizer. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106347 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 23:11:35 +00:00
Evan Cheng
86050dc8cc Allow ARM if-converter to be run after post allocation scheduling. 
- This fixed a number of bugs in if-converter, tail merging, and post-allocation
  scheduler. If-converter now runs branch folding / tail merging first to
  maximize if-conversion opportunities.
- Also changed the t2IT instruction slightly. It now defines the ITSTATE
  register which is read by instructions in the IT block.
- Added Thumb2 specific hazard recognizer to ensure the scheduler doesn't
  change the instruction ordering in the IT block (since IT mask has been
  finalized). It also ensures no other instructions can be scheduled between
  instructions in the IT block.

This is not yet enabled.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106344 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 23:09:54 +00:00
Jim Grosbach
ef6eb9c7ab back-end libcall handling for ATOMIC_SWAP (__sync_lock_test_and_set) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106342 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 23:03:10 +00:00
Jim Grosbach
68741be5e6 Enable Expand handling of atomics for subtargets that can't do them inline. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106336 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 22:35:32 +00:00
Bruno Cardoso Lopes
4b8921d1c7 Use the new 'defm' class inheritance in SSE 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106327 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 22:10:11 +00:00
Bob Wilson
ebe99b2c19 Rewrite chained if's as switches and replace assertions with llvm_unreachable 
(as suggested in radar 8104405).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106318 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 21:32:42 +00:00
Dale Johannesen
51bd47edbc Fix ARM/Thumb reversal in previous attempt. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106314 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 21:07:47 +00:00
Jakob Stoklund Olesen
52c61ec164 When using ADDri to get the address of a stack object, 255 is a conservative 
limit on the offset that can be materialized without using the register
scavenger.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106312 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 20:59:25 +00:00
Dan Gohman
1415a602ad Make this comment less specific. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106311 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 20:45:41 +00:00
Dan Gohman
ea9f151cbc Fix X86FastISel's address-mode folding to stay within the 
original basic block. This avoids trouble with examining
instructions in other basic blocks which haven't been
assigned registers yet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106310 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 20:44:47 +00:00
Dale Johannesen
10416803c1 An attempt to fix the problem Anton reported with 
ARM tail calls.  Don't know if it works, but it
doesn't break Darwin.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106309 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 20:44:28 +00:00
Dale Johannesen
c66cdf74a9 Enable tail calls on ARM by default, with some 
basic tests.

This has been well tested on Darwin but not elsewhere.
It should work provided the linker correctly resolves
  B.W  <label in other function>
which it has not seen before, at least from llvm-based
compilers.  I'm leaving the arm-tail-calls switch in
until I see if there's any problems because of that;
it might need to be disabled for some environments.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106299 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 19:00:18 +00:00
Dan Gohman
a606d955de Start TargetRegisterClass indices at 0 instead of 1, so that 
MachineRegisterInfo doesn't have to confusingly allocate an extra
entry.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106296 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 18:13:55 +00:00
Dale Johannesen
df50d7e238 Last round of changes for ARM tail calls. 
Not turning them on yet.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106295 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 18:13:11 +00:00
Jakob Stoklund Olesen
0d8ba3303b Treat the ARM inline asm {cc} constraint as a physreg (%CPSR), just like X86 
does for {flags}. If we create virtual registers of the CCR class, RegAllocFast
may try to spill them, and we can't do that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106289 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 16:49:33 +00:00
Dan Gohman
027657db7c Change UpdateNodeOperands' operand and return value from SDValue to 
SDNode *, since it doesn't care about the ResNo value.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106282 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 15:30:29 +00:00
Dan Gohman
5ff12fc41a Delete unused variables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106280 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 14:32:32 +00:00
Dan Gohman
e368b460a2 Eliminate unnecessary uses of getZExtValue(). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106279 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 14:22:04 +00:00
Dan Gohman
7720cb3823 isValueValidForType can be a static member function. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106278 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 14:01:07 +00:00
Eric Christopher
f627dc37bf Some assorted isTwoAddress -> Constraints cleanup. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106273 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 02:41:19 +00:00
Dan Gohman
e54081088e Don't maintain a set of deleted nodes; instead, use a HandleSDNode 
to track a node over CSE events. This fixes PR7368.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106266 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 01:24:29 +00:00
Bruno Cardoso Lopes
d7f9cc4de7 Add {mix,max}{ss,sd}{rr,rm} AVX forms. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106264 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 01:12:56 +00:00
Dan Gohman
8a7f7426ee Fold the ShrinkDemandedOps pass into the regular DAGCombiner pass, 
which is faster, simpler, and less surprising.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106263 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 01:05:21 +00:00
Bruno Cardoso Lopes
597ec8ed51 Use new tablegen resources in SSE tablegen code. This will 
be done incrementally and intermixed with the adding of more
AVX instructions. This is a first step in that direction


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106251 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-17 23:05:30 +00:00
Stuart Hastings
3bf9125933 Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). This 
addresses a longstanding deficiency noted in many FIXMEs scattered
across all the targets.

This effectively moves the problem up one level, replacing eleven
FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path
through FastISel where we actually supply a DebugLoc, fixing Radar
7421831.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106243 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-17 22:43:56 +00:00
Jim Grosbach
7072cf62a5 Thumb1 and any pre-v6 ARM target should use the libcall expansion of 
ISD::MEMBARRIER. v7 and v7 ARM mode continue to use the custom lowering.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106204 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-17 02:02:03 +00:00
Jim Grosbach
c73993b678 simplify code a bit and add a more explanatory assert for cases that 
previously would result in 'cannot yet select' errors.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106199 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-17 01:37:00 +00:00
Eric Christopher
e98ad83543 Hack to let the move lowering handle dynamic-no-pic absolute moves of 
TLVP:

movl _a@TLVP, %eax

Daniel: Please review if you get a chance.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106194 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-17 00:51:48 +00:00
Jim Grosbach
7616b646f1 format and 80-column cleanup 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106173 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-16 23:45:49 +00:00
Jakob Stoklund Olesen
a2846b4bee Don't attempt preserving conservative kill flags. We were doing it wrong. 
This is before LiveVariables anyway, where these kill flags are recalculated.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106157 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-16 22:11:08 +00:00
Bob Wilson
07f6e805b1 Remove the hidden "neon-reg-sequence" option. The reg sequences are working 
now, so there's no need to disable them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106155 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-16 21:34:01 +00:00
Benjamin Kramer
0f471e018f TODO-- 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106102 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-16 15:47:00 +00:00
Evan Cheng
46df4eb46e Make post-ra scheduling, anti-dep breaking, and register scavenger (conservatively) aware of predicated instructions. This enables ARM to move if-conversion before post-ra scheduler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106091 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-16 07:35:02 +00:00
Bill Wendling
d361a77f14 Create a more targeted fix for not sinking instructions into a range where it 
will conflict with another live range. The place which creates this scenerio is
the code in X86 that lowers a select instruction by splitting the MBBs. This
eliminates the need to check from the bottom up in an MBB for live pregs.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106066 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-15 23:46:31 +00:00
Eric Christopher
6102549737 For 32-bit non-pic tlv mach-o addressing we don't need a pic base or 
a relative address.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106064 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-15 23:08:42 +00:00
Dale Johannesen
38d5f0441c Add file missing from previous commit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106058 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-15 22:24:08 +00:00
Dale Johannesen
6470a116f1 Next round of tail call changes. Register used in a tail 
call must not be callee-saved; following x86, add a new
regclass to represent this.  Also fixes a couple of bugs.
Still disabled by default; Thumb doesn't work yet.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106053 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-15 22:08:33 +00:00
Dale Johannesen
bf37850e42 Reapply 105986 with fix for bug pointed out by Jakob: 
flag argument to addReg is not the same format as flags attached
to MachineOperand, although both have the same info.  I don't
think this actually mattered; the bootstrap failure did not
reproduce on the next run anyway.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106049 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-15 21:36:43 +00:00
Chris Lattner
868ee9460c fix fastisel to handle GS and FS relative pointers. Patch by 
Nelson Elhage!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106031 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-15 19:08:40 +00:00
Bob Wilson
827b2106fe Add basic support for NEON modified immediates besides VMOV. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106030 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-15 19:05:35 +00:00
Daniel Dunbar
f4a7bf4ec3 Add <cstddef> include to get ptrdiff_t, for gcc-4.6; patch by Dimitry Andric. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105994 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-15 14:50:42 +00:00