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16869 Commits

Author SHA1 Message Date
Eric Christopher
c0394c0b8c Make this happen for ARM like x86. Don't entirely bail out when 
an address is in a different block, get it into a register and go
from there.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118936 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-12 22:52:32 +00:00
Evan Cheng
875a6ac09a Add conditional mvn instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118935 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-12 22:42:47 +00:00
Jim Grosbach
e1634e9351 Zap a copy/paste-o bit of dead code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118926 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-12 21:29:10 +00:00
Jim Grosbach
2716e25c2c Refactor to parameterize some ARM load/store encoding patterns. Preparatory 
to splitting the load/store pre/post indexed instructions into [r, r] and
[r, imm] forms.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118925 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-12 21:28:15 +00:00
Owen Anderson
5de6d841a5 First stab at providing correct Thumb2 encodings, start with adc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118924 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-12 21:12:40 +00:00
Evan Cheng
529916ca4a Add some missing isel predicates on def : pat patterns to avoid generating VFP vmla / vmls (they cause stalls). Disabling them in isel is properly not a right solution, I'll look into a proper solution next. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118922 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-12 20:32:20 +00:00
Jim Grosbach
b39e6488ee Kill more unused stuff. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118921 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-12 19:27:45 +00:00
Jim Grosbach
a0a6a47c02 Remove unused class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118919 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-12 19:24:53 +00:00
Dan Gohman
52668c9a30 When the definition of an address value is in a different block 
from the user of the address, fall back to just using the
address in a register instead of bailing out of fast-isel
altogether.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118917 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-12 19:14:00 +00:00
Chris Lattner
269f10b316 accept lret as an alias for lretl, fixing the reopened part of PR8592 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118916 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-12 18:54:56 +00:00
Jim Grosbach
d75c3f136b Fill in the default predication bits for ARM unconditional branch. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118907 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-12 18:13:26 +00:00
Jim Grosbach
80f9e6724f Encoding for ARM LDRSB instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118905 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-12 17:52:59 +00:00
Chris Lattner
6b5e3978e3 implement PR8592: empirically "lretq" is a "lret" with a rex.w prefix. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118903 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-12 17:41:20 +00:00
Chris Lattner
a29aae7aca tidy up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118896 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-12 17:24:29 +00:00
Kalle Raiskila
7ea1ab5f41 Fix memory access lowering on SPU, adding 
support for the case where alignment<value size.

These cases were silently miscompiled before this patch.
Now they are overly verbose -especially storing is- and
any front-end should still avoid misaligned memory 
accesses as much as possible. The bit juggling algorithm
added here probably has some room for improvement still.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118889 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-12 10:14:03 +00:00
Eric Christopher
d0c82a683e Fix up a few more spots of addrmode2 (or not) changes that were 
missed. Update some comments accordingly.

Fixes rdar://8652289


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118888 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-12 09:48:30 +00:00
Dale Johannesen
0e03456a65 Remove possibly useful info from comment, per Chris. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118865 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-12 00:43:18 +00:00
Bruno Cardoso Lopes
7d5652dcd5 Enable mips32 mul instruction. Patch by Akira Hatanaka <ahatanaka@mips.com> 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118864 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-12 00:38:32 +00:00
Jim Grosbach
e50e6bcd90 Start of support for binary emit of 16-it Thumb instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118859 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-11 23:41:09 +00:00
Owen Anderson
8f14391314 Fill out support for Thumb2 encodings of NEON instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118854 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-11 23:12:55 +00:00
Wesley Peck
48bcda4dd6 The BRK instruction in the MicroBlaze is a branch-and-link. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118848 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-11 22:21:08 +00:00
Wesley Peck
ef5b390263 Fix tblgen instruction errors exposed by MC asm parser tests 
Fix minimum 16-bit signed value error exposed by MC asm parser tests
Add initial MC asm parser tests for the MBlaze backend


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118844 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-11 21:40:53 +00:00
Owen Anderson
57dac88f77 Add correct Thumb2 encodings for NEON vst[1,2,3,4] and vld[1,2,3,4]. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118843 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-11 21:36:43 +00:00
Eric Christopher
79ab2fe01a Revert the accidental commit I made reverting the previous commit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118835 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-11 20:50:14 +00:00
Jim Grosbach
d1d5a39cad ARM fixup encoding for direct call instructions (BL). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118829 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-11 20:05:40 +00:00
Eric Christopher
6c50119ba3 Revert this temporarily. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118827 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-11 19:47:02 +00:00
Eric Christopher
391f228e7e Change the prologue and epilogue to use push/pop for the low ARM registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118823 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-11 19:26:03 +00:00
Owen Anderson
c7139a6f0d Add support for Thumb2 encodings of NEON data processing instructions, using the new PostEncoderMethod infrastructure. 
More tests to come.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118819 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-11 19:07:48 +00:00
Wesley Peck
60f923c5e2 Fixed some bugs in MBlaze asm parser that were introduced when removing OwningPtrs from the code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118807 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-11 18:41:33 +00:00
Chris Lattner
af510f16ec add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118806 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-11 18:23:57 +00:00
Jim Grosbach
c466b937db Encoding of destination fixup for ARM branch and conditional branch 
instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118801 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-11 18:04:49 +00:00
Chris Lattner
1e68fdb946 add pr# 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118797 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-11 17:17:56 +00:00
Jim Grosbach
7eab97f260 Encoding for ARM LDRSH_POST. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118794 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-11 16:55:29 +00:00
Rafael Espindola
3f2d13c98e Remove some explicit arguments to getELFSection. This is 
a leftover from the removal of isExplicit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118774 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-11 03:40:25 +00:00
Jim Grosbach
928f3325a7 Encoding for ARM LDRSH and LDRSH_PRE. Cannonicalize operand names. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118767 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-11 01:55:59 +00:00
Jim Grosbach
d507d1f616 Fix encoding of Ra register for ARM smla* instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118761 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-11 01:27:41 +00:00
Jim Grosbach
570a922691 ARM STRH encoding information. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118757 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-11 01:09:40 +00:00
Jim Grosbach
954ffff79b Move LDM predicate operand encoding into base clase. Add STM missing STM 
encoding bits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118738 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-10 23:44:32 +00:00
Jim Grosbach
5d5eb9e381 ARM LDM encoding for the mode (ia, ib, da, db) operand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118736 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-10 23:38:36 +00:00
Jim Grosbach
c1235e2a4e Fix ARM encoding of non-return LDM instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118732 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-10 23:18:49 +00:00
Jim Grosbach
866aa394ca Fix ARM encoding of LDM+Return instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118730 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-10 23:12:48 +00:00
Nate Begeman
bf5be2654e Fix an issue where we tried to turn a v2f32 build_vector into a v4i32 build vector with 2 elts 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118720 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-10 21:35:41 +00:00
Jim Grosbach
7c7ddb21c3 Simplify and clean up MC symbol lookup for ARM constant pool values. This fixes 
double quoting of ObjC symbol names in constant pool entries.

rdar://8652107

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118688 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-10 17:59:10 +00:00
Jim Grosbach
2c4d5125c7 Update ARMConstantPoolValue to not use a modifier string. Use an explicit 
VariantKind marker to indicate the additional information necessary. Update
MC to handle the new Kinds. rdar://8647623



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118671 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-10 03:26:07 +00:00
Bruno Cardoso Lopes
c4bb67c8d9 Add clo instruction. Patch by Akira Hatanaka (ahatanaka@mips.com) with some minor tweaks 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118667 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-10 02:13:22 +00:00
Bill Wendling
8ea974039a Emit a '!' if this is a "writeback" register or memory address. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118662 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-10 01:07:54 +00:00
Matt Beaumont-Gay
cc8d10e1a8 Rename a parameter to avoid confusion with a local variable 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118656 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-10 00:08:58 +00:00
Bill Wendling
8e8b18bcfa Emit the warning about the register list not being in ascending order only once. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118653 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-09 23:45:59 +00:00
Bill Wendling
5fa22a1975 s/std::vector/SmallVector/ 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118648 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-09 23:28:44 +00:00
Bill Wendling
c3236753d6 Delete the allocated vector. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118644 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-09 22:51:42 +00:00