and output the dwarf line number tables. This contains the code to emit and
encode the dwarf line tables from the previously gathered information in the
MCLineSection objects. This contains all the details to encode the line and
address deltas into the dwarf line table.
To do this an MCDwarfLineAddrFragment has been added.
Also this moves the interface code out of Mach-O streamer into
MCDwarf so it should be useable by other object file formats.
There is now one call to be made from an MCObjectStreamer
EmitInstruction() method:
MCLineEntry::Make(this, getCurrentSection());
to create a line entry after each instruction is assembled.
And one call call to be made from an MCObjectStreamer Finish() method:
MCDwarfFileTable::Emit(this, DwarfLineSection);
when getContext().hasDwarfFiles() is true and is passed a object file specific
MCSection where to emit the dwarf file and the line tables.
This appears to now be correct for 32-bit targets, at least x86. But the
relocation entries for 64-bit Darwin needs some further work which is next
up to work on. So for now the 64-bit Mach-O target does not output the
dwarf file and line tables.
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if we are given a Layout object, even in cases when the value is not fixed.
This will be needed by the final patch for the dwarf .loc support to size a
new MCDwarf fragment needed to build and emit dwarf line number tables.
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time. That way, the EntrySize field is initialized for other code paths,
namely, the .ll -> .o code path.
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With this patch in
movq $foo, foo(%rip)
foo:
.long foo
We produce a R_X86_64_32S for the first relocation and R_X86_64_32 for the
second one.
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resolved or not. Different object files have different restrictions and
different native assemblers have different idiosyncrasies we want to emulate
for now.
Move the existing MachO logic to the new place and implement an ELF one that
gets fixups to globals right.
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the eqv X86 class.
For now, I split the ELFARMAsmBackend from the DarwinARMAsmBackend
(also mimicking X86)
Tested against -r115126
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or not. TableGen needs to generate the printInstruction() function as taking
an MCInstr* or a MachineInstr*, depending. Default to the old non-MC
version so that everything not yet using MC continues to just work without
fidding.
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1. Cortex-a9 8-bit and 16-bit loads / stores AGU cycles are 1 cycle longer than 32-bit ones.
2. Cortex-a9 is out-of-order so model all read cycles as cycle 1.
3. Lots of other random fixes for A8 and A9.
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hide jump threading opportunities by turning control flow into data flow. Run an early JumpThreading pass
(adds approximately an additional 1% to optimization time on SPEC), allowing it to get a shot at these cases
first. Fixes <rdar://problem/8447345>.
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Because of this, we cannot use the Simplify* APIs, as they can assert-fail on unreachable code. Since it's not easy to determine
if a given threading will cause a block to become unreachable, simply defer simplifying simplification to later InstCombine and/or
DCE passes.
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