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9c09c9ec9d
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1175 Commits

Author SHA1 Message Date
Chris Lattner
9c09c9ec9d teach the ppc backend how to spill/reload vector regs 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26806 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-16 22:24:02 +00:00
Chris Lattner
419ed53006 add callee saved vector regs 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26805 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-16 22:07:06 +00:00
Evan Cheng
714554d707 Added a way for TargetLowering to specify what values can be used as the 
scale component of the target addressing mode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26802 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-16 21:47:42 +00:00
Chris Lattner
8aa777d5ea in functions that use a lot of callee saved regs, this can be more than 
5 instructions away.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26801 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-16 21:31:45 +00:00
Chris Lattner
335fd3c7c2 Add support for copying registers. still needed: spilling and reloading them 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26800 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-16 20:03:58 +00:00
Nate Begeman
2df992883b Another case we could do better on. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26795 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-16 18:50:44 +00:00
Chris Lattner
4bb1895072 Save/restore VRSAVE once per function, not once per block. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26793 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-16 18:25:23 +00:00
Nate Begeman
133decdceb Update scheduling info for vrsave instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26776 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-15 05:25:05 +00:00
Chris Lattner
a08610c8a5 Fix an off by one error that caused PPC LLC failures last night. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26758 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-14 17:56:49 +00:00
Evan Cheng
9c543b2299 PPC LSR pass should use target lowering hooks. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26743 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-13 23:56:51 +00:00
Evan Cheng
c4c6257c1a Added getTargetLowering() to TargetMachine. Refactored targets to support this. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26742 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-13 23:20:37 +00:00
Chris Lattner
1877ec9b02 For functions that use vector registers, save VRSAVE, mark used 
registers, and update it on entry to each function, then restore it on exit.

This compiles:

void func(vfloat *a, vfloat *b, vfloat *c) {
        *a = *b * *c + *c;
}

to this:

_func:
        mfspr r2, 256
        oris r6, r2, 49152
        mtspr 256, r6
        lvx v0, 0, r5
        lvx v1, 0, r4
        vmaddfp v0, v1, v0, v0
        stvx v0, 0, r3
        mtspr 256, r2
        blr

GCC produces this (which has additional stack accesses):

_func:
        mfspr r0,256
        stw r0,-4(r1)
        oris r0,r0,0xc000
        mtspr 256,r0
        lvx v0,0,r5
        lvx v1,0,r4
        lwz r12,-4(r1)
        vmaddfp v0,v0,v1,v0
        stvx v0,0,r3
        mtspr 256,r12
        blr


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26733 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-13 21:52:10 +00:00
Chris Lattner
64ce964673 Fix a couple of bugs that broke the alpha tester build 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26722 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-13 05:23:59 +00:00
Chris Lattner
3faad495bc Handle cracked instructions in dispatch group formation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26721 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-13 05:20:04 +00:00
Chris Lattner
fd97734f36 Mark instructions that are cracked by the PPC970 decoder as such. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26720 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-13 05:15:10 +00:00
Chris Lattner
88d211f823 Several big changes: 
1. Use flags on the instructions in the .td file to indicate the PPC970 unit
   type instead of a table in the .cpp file.  Much cleaner.
2. Change the hazard recognizer to build d-groups according to the actual
   algorithm used, not my flawed understanding of it.
3. Model "must be in the first slot" and "must be the only instr in a group"
   accurately.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26719 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-12 09:13:49 +00:00
Chris Lattner
9c2c38674a blr is a branch too 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26710 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-11 21:49:49 +00:00
Chris Lattner
e928a72772 teach the JIT to encode vector registers 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26697 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-10 20:19:50 +00:00
Chris Lattner
b0d21ef20c Change the interface for getting a target HazardRecognizer to be more clean. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26608 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-08 04:25:59 +00:00
Chris Lattner
49f398b96a add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26605 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-08 00:25:47 +00:00
Jim Laskey
7809811e4e Use "llvm.metadata" section for debug globals. Filter out these globals in the 
asm printer.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26599 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-07 22:00:35 +00:00
Chris Lattner
b84225b080 add another missing store. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26595 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-07 16:26:48 +00:00
Chris Lattner
ab5801cb28 add a couple more load/store instrs, add a newline to the end of file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26594 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-07 16:19:46 +00:00
Nate Begeman
3acbe5d4f0 This kinda sorta implements "things that have to lead a dispatch group". 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26591 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-07 08:30:27 +00:00
Chris Lattner
2046371e70 add some new instructions to the classifier. With this, we correctly insert 
a nop into Freebench/neural, which speeds it up from 136->129s (~5.4%).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26590 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-07 07:14:55 +00:00
Chris Lattner
7ce64852e8 add some comments that describe what we model 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26588 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-07 06:44:19 +00:00
Chris Lattner
c664418820 Implement a very very simple hazard recognizer for LSU rejects and ctr set/read 
flushes


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26587 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-07 06:32:48 +00:00
Chris Lattner
5a63c47fb5 add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26585 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-07 04:42:59 +00:00
Chris Lattner
bbf1c72d51 implement TII::insertNoop 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26562 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-05 23:49:55 +00:00
Chris Lattner
9601a86a64 Copysign needs to be expanded everywhere. Note that Alpha and IA64 should 
implement copysign as a native op if they have it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26541 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-05 05:08:37 +00:00
Chris Lattner
0f6ab6ff97 Implement CodeGen/PowerPC/or-addressing-mode.ll, which is also PR668. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26450 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-01 07:14:48 +00:00
Chris Lattner
00d18f0879 add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26448 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-01 06:36:20 +00:00
Chris Lattner
5126984b1d Compile this: 
void foo(float a, int *b) { *b = a; }

to this:

_foo:
        fctiwz f0, f1
        stfiwx f0, 0, r4
        blr

instead of this:

_foo:
        fctiwz f0, f1
        stfd f0, -8(r1)
        lwz r2, -4(r1)
        stw r2, 0(r4)
        blr

This implements CodeGen/PowerPC/stfiwx.ll, and also incidentally does the
right thing for GCC bugzilla 26505.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26447 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-01 05:50:56 +00:00
Chris Lattner
8c13d0a573 Use a target-specific dag-combine to implement CodeGen/PowerPC/fp-int-fp.ll. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26445 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-01 04:57:39 +00:00
Evan Cheng
d30bf01e90 Vector op lowering. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26438 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-01 01:11:20 +00:00
Chris Lattner
bf751e2d6f Add a subtarget feature for the stfiwx instruction. I know the G5 has it, 
but I don't know what other PPC impls do.  If someone could update the proc
table, I would appreciate it :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26421 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-28 07:08:22 +00:00
Chris Lattner
f4c8575c27 remove implemented item 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26418 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-28 06:36:04 +00:00
Nate Begeman
6e53ceb0d4 readme updates 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26405 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-27 22:08:36 +00:00
Chris Lattner
2c003e26e5 Add memory printing support for PPC. Input memory operands now work with 
inline asms! :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26365 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-24 20:27:40 +00:00
Chris Lattner
e5d8861126 Implement selection of inline asm memory operands 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26348 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-24 02:13:12 +00:00
Evan Cheng
d0839f3071 PPC JIT relocation model should be DynamicNoPIC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26338 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-23 22:18:07 +00:00
Chris Lattner
e3f01570c1 Implement the PPC inline asm "L" modifier. This allows us to compile: 
long long test(long long X) {
  __asm__("foo %0 %L0 %1 %L1" : "=r"(X): "r"(X));
  return X;
}

to:
        foo r2 r3 r2 r3


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26333 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-23 19:31:10 +00:00
Evan Cheng
4c1aa86657 - Added option -relocation-model to set relocation model. Valid values include static, pic, 
dynamic-no-pic, and default.
PPC and x86 default is dynamic-no-pic for Darwin, pic for others.
- Removed options -enable-pic and -ppc-static.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26315 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-22 20:19:42 +00:00
Jim Laskey
0420f2aaf9 Coordinate activities with llvm-gcc4 and dwarf. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26314 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-22 19:02:11 +00:00
Chris Lattner
1efa40f6a4 split register class handling from explicit physreg handling. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26308 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-22 00:56:39 +00:00
Chris Lattner
4217ca8dc1 Updates to match change of getRegForInlineAsmConstraint prototype 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26305 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-21 23:11:00 +00:00
Evan Cheng
d2ee218b49 Moved PICEnabled to include/llvm/Target/TargetOptions.h 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26272 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-18 00:08:58 +00:00
Nate Begeman
551bf3f800 kill ADD_PARTS & SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBC 
and SUBE nodes that actually expose what's going on and allow for
significant simplifications in the targets.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26255 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-17 05:43:56 +00:00
Evan Cheng
298ebf2bd8 If the false case is the current basic block, then this is a self loop. 
We do not want to emit "Loop: ... brcond Out; br Loop", as it adds an extra
instruction in the loop.  Instead, invert the condition and emit
"Loop: ... br!cond Loop; br Out.

Generalize the fix by moving it from PPCDAGToDAGISel to SelectionDAGLowering.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26231 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-16 08:27:56 +00:00
Chris Lattner
0d7db6f79a If we have zero initialized data with external linkage, use .zerofill to 
emit it (instead of .space), saving a bit of space in the .o file.

For example:
int foo[100];
int bar[100] = {};

when compiled with C++ or -fno-common results in shrinkage from 1160 to 360
bytes of space.  The X86 backend can also do this on darwin.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26185 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-14 22:18:23 +00:00