6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-10-30 16:17:05 +00:00
Code Issues Projects Releases Wiki Activity
86,978 Commits 39 Branches 0 Tags
9e3c3886d0b42b80f9eb38067fa85d96c75a4ec5
Commit Graph

393 Commits

Author SHA1 Message Date
Owen Anderson
9f666b5f2e CPS instructions are UNPREDICTABLE inside IT blocks. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140102 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 23:47:10 +00:00
Owen Anderson
04c7877894 Thumb2 TBB and TBH instructions are only allowed at the end of IT blocks, not in the middle. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140079 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 22:34:23 +00:00
Jim Grosbach
7f739bee26 Thumb2 assembly parsing and encoding for TBB/TBH. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140078 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 22:21:13 +00:00
Owen Anderson
ecd1c55790 Handle STRT (and friends) like LDRT (and friends) for decoding purposes. Port over additional encoding tests to decoding tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140032 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 18:07:10 +00:00
Owen Anderson
cb77551927 Bitfield mask instructions are unpredictable if the encoded LSB is higher than the encoded MSB. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139972 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 23:30:01 +00:00
Owen Anderson
8b22778431 Fix bitfield decoding based on Eli's feedback. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139969 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 23:04:48 +00:00
Owen Anderson
e4f2df945a Thumb2 pre-indexed loads/stores use the restricted GPR set for Rt. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139965 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 22:42:36 +00:00
Owen Anderson
89db0f690c Fix disassembly of Thumb2 BFI instructions with bit range of [0, 32). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139964 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 22:29:48 +00:00
Owen Anderson
705b48ff86 Fix disassembly of Thumb2 LDRSH with a #-0 offset. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139943 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 21:08:33 +00:00
Owen Anderson
98c5ddabca Don't attach annotations to MCInst's. Instead, have the disassembler return, and the printer accept, an annotation string which can be passed through if the client cares about annotations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139876 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-15 23:38:46 +00:00
Owen Anderson
34626acf7f Nested IT blocks are UNPREDICTABLE. Mark them as such when disassembling them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139736 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-14 21:06:21 +00:00
Owen Anderson
a3157b4026 Port more encoding tests to decoding tests, and correct an improper Thumb2 pre-indexed load decoding this uncovered. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139522 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-12 18:56:30 +00:00
Owen Anderson
921d01ae1f LDM writeback is not allowed if Rn is in the target register list. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139432 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 23:13:33 +00:00
Owen Anderson
08fef885eb Fix assembly/disassembly of Thumb2 ADR instructions with immediate operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139422 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 22:24:36 +00:00
Owen Anderson
51f6a7abf2 Thumb unconditional branches are allowed in IT blocks, and therefore should have a predicate operand, unlike conditional branches. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139415 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 21:48:23 +00:00
Jim Grosbach
b6aed508e3 Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139381 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 18:37:27 +00:00
Owen Anderson
441462f932 All conditional branches are disallowed in IT blocks, not just CBZ/CBNZ. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139329 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 22:48:37 +00:00
Owen Anderson
d2fc31b3f7 Soft fail CBZ/CBNZ in the disassembler if they appear inside an IT block. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139328 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 22:42:49 +00:00
Jim Grosbach
a77295db19 Thumb2 assembly parsing and encoding for LDRD(immediate). 
Refactor operand handling for STRD as well. Tests for that forthcoming.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139322 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 22:07:06 +00:00
Owen Anderson
170580e8f4 Remove the "common" set of instructions shared between ARM and Thumb2 modes. This is no longer needed now that Thumb2 has its own copy of the STC/LDC instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139268 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 00:11:18 +00:00
Owen Anderson
8a83f71301 Create Thumb2 versions of STC/LDC, and reenable the relevant tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139256 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-07 21:10:42 +00:00
James Molloy
a5d5856854 Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139250 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-07 19:42:28 +00:00
Owen Anderson
6de3c6f1a9 Port more assembler tests over to disassembler tests, and fix a minor logic error that exposed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139240 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-07 17:55:19 +00:00
James Molloy
b950585cc5 Refactor instprinter and mcdisassembler to take a SubtargetInfo. Add -mattr= handling to llvm-mc. Reviewed by Owen Anderson. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139237 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-07 17:24:38 +00:00
Owen Anderson
a1c110045a Merge the ARM disassembler header into the implementation file, since it is not externally exposed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138982 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-01 23:35:51 +00:00
Owen Anderson
a6804444e8 Fix 80 columns violations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138980 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-01 23:23:50 +00:00
James Molloy
c047dcade5 Fix up r137380 based on post-commit review by Jim Grosbach. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138948 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-01 18:02:14 +00:00
Owen Anderson
b45b11bce1 The asm parser currently selects the wrong encoding for non-conditional Thumb2 branches. However, this exposed a number of situations where the decoder was too permissive in allowing invalid instructions to decode successful. Specify additional fixed bits to close those gaps. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138910 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-31 22:00:41 +00:00
Owen Anderson
eaca928a37 Fix issues with disassembly of IT instructions involving condition codes other the EQ/NE. Discovered by roundtrip testing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138840 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-30 22:58:27 +00:00
Owen Anderson
f1eab597b2 Improve encoding support for BLX with immediat eoperands, and fix a BLX decoding bug this uncovered. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138675 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-26 23:32:08 +00:00
Owen Anderson
9f7e831994 Spelling fail. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138667 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-26 21:47:57 +00:00
Owen Anderson
9ab0f25fc1 invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138653 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-26 20:43:14 +00:00
Owen Anderson
1af7f7291d Update for feedback from Jim. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138642 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-26 19:39:26 +00:00
Benjamin Kramer
86ce852a15 ARMDisassembler: Always return a size, even when disassembling fails. 
This should fix PR10772.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138636 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-26 18:21:36 +00:00
Owen Anderson
96425c8464 Support an extension of ARM asm syntax to allow immediate operands to ADR instructions. This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138635 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-26 18:09:22 +00:00
Owen Anderson
9bd655dcde Fix PR10755 by checking for invalid predicate codes from UNPREDICTABLE t2IT instructions when decoding their successors. 
This is the last disassembly crash detected by exhaustive Thumb2 instruction space.  Major thanks to Chandler Carruth for making this kind of exhaustive testing possible.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138625 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-26 06:19:51 +00:00
Owen Anderson
99906830e8 Port over additional encoding tests to decoding tests, and fix an operand ordering bug this exposed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138575 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-25 18:30:18 +00:00
Owen Anderson
f44082091c Perform more thorough checking of t2IT mask parameters, which fixes all remaining crashers when disassembling the entire 16-bit instruction space. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138507 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-24 22:40:22 +00:00
Owen Anderson
12a1e3bbcb Be careful not to walk off the end of the operand info list while updating VFP predicates. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138492 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-24 21:35:46 +00:00
Evan Cheng
3e74d6fdd2 Move TargetRegistry and TargetSelect from Target to Support where they belong. 
These are strictly utilities for registering targets and components.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138450 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-24 18:08:43 +00:00
Owen Anderson
e234d02204 Be stricter in enforcing IT instruction predicate values, so that we don't end up trying to print out an illegal predicate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138443 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-24 17:21:43 +00:00
Owen Anderson
82265a2c72 Fix decoding of Thumb2 prefetch instructions, which account for all the remaining Thumb2 decoding failures found by randomized testing so far. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138341 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-23 17:51:38 +00:00
Owen Anderson
6153a036f5 Fix Thumb2 decoding of CPS instructions to mirror ARM decoding of the same instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138339 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-23 17:45:18 +00:00
Owen Anderson
8e1e60b5f8 Reject invalid imod values in t2CPS instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138306 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 23:44:04 +00:00
Owen Anderson
357ec6850b Fix decoding of VMOVSRR and VMOVRRS, which account for the overwhelming majority of decoder crashes detected by randomized testing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138269 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 20:27:12 +00:00
Owen Anderson
2cbf210450 Fix another batch of VLD/VST decoding crashes discovered by randomized testing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138255 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 18:42:13 +00:00
Owen Anderson
f1c8e3e70e Correct writeback handling of duplicating VLD instructions. Discovered by randomized testing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138251 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 18:22:06 +00:00
Owen Anderson
b113ec55e8 Fix an incorrect shift when decoding SP-relative stores in Thumb1-mode. Add more tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138246 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 17:56:58 +00:00
Owen Anderson
78affc9ea1 STC2L_POST and STC2L_POST should be handled the same as STCL_POST/LDC_POST for the purposes of decoding all operands except the predicate. 
Found by randomized testing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138003 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-18 22:47:44 +00:00
Owen Anderson
846dd95f87 Fix the decoding of RFE instruction. RFEs have the load bit set, while SRSs have it unset. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138000 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-18 22:31:17 +00:00