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4 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
61396aebee Fix a batch of x86 tests to be coalescer independent. 
Most of these tests require a single mov instruction that can come either before
or after a 2-addr instruction. -join-physregs changes the behavior, but the
results are equivalent.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130891 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-04 23:54:51 +00:00
Dan Gohman
e5dacc55ad Use a 32-bit and with implicit zero-extension instead of a 64-bit and if it 
has an immediate with at least 32 bits of leading zeros, to avoid needing to
materialize that immediate in a register first.

FileCheckize, tidy, and extend a testcase to cover this case.

This fixes rdar://7527390.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93160 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-11 17:58:34 +00:00
Dan Gohman
36a0947820 Eliminate more uses of llvm-as and llvm-dis. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81290 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-08 23:54:48 +00:00
Chris Lattner
d0ba2a9c14 Compile x86-64-and-mask.ll into: 
_test:
	movl	%edi, %eax
	ret

instead of:

_test:
        movl    $4294967295, %ecx
        movq    %rdi, %rax
        andq    %rcx, %rax
        ret

It would be great to write this as a Pat pattern that used subregs 
instead of a 'pseudo' instruction, but I don't know how to do that
in td files.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47658 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-27 05:47:54 +00:00