code. It used to #include the enhanced disassembly
information for the targets it supported straight
out of lib/Target/{X86,ARM,...} but now it uses a
new interface provided by MCDisassembler, and (so
far) implemented by X86 and ARM.
Also removed hacky #define-controlled initialization
of targets in edis. If clients only want edis to
initialize a limited set of targets, they can set
--enable-targets on the configure command line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101179 91177308-0d34-0410-b5e6-96231b3b80d8
after edis. Really, there ought to be some
mechanism to ensure that PARALLEL_DIRS get built
after DIRS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101095 91177308-0d34-0410-b5e6-96231b3b80d8
libEnhancedDisassembly, so we now build the
static library in all cases (although the shared
library is only built when requested/possible).
Also, fixed a bug where edis wasn't properly
initializing the targets it uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101072 91177308-0d34-0410-b5e6-96231b3b80d8
time I use the LIBS variable, which is not subject
to a %.a -> -l% transformation, to link llvm-mc
against libEnhancedDisassembly.
llvm-mc -edis works the same as llvm-mc
-disassemble, but outputs tokens and operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101058 91177308-0d34-0410-b5e6-96231b3b80d8
state was being executed too lazily, and the LLVM
assembly syntax for the disassembler was not being
written into the proper disassembler state variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100830 91177308-0d34-0410-b5e6-96231b3b80d8
I also added a rule to the ARM target's Makefile to
build the ARM-specific instruction information table
for the enhanced disassembler.
I will add the test harness for all this stuff in
a separate commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100735 91177308-0d34-0410-b5e6-96231b3b80d8
argument that had to be between 0 and 7 to have any value,
firing an assert later in the AsmPrinter. Now, the
disassembler rejects instructions with out-of-range values
for that immediate.
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return an error status in all failure cases, printing
messages to debugs() only when debugging is enabled.
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on Mac OS X to use @rpath rather than an absolute
path. Also allowed the version to be set using an
environment variable.
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whose opcodes extend into the ModR/M field using the
Form field of the instruction rather than by special
casing each instruction. Commented out the special
casing of VMCALL, which is the first instruction to use
this special form. While I was in the neighborhood,
added a few comments for people modifying the Intel
disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96043 91177308-0d34-0410-b5e6-96231b3b80d8
operand into the CodeGenInstruction's list of operands,
which is useful for EDEmitter. (Still working on PR6219)
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implementation. Also changed the constructor
so that it does not require a Record, making it
usable by the EDEmitter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95715 91177308-0d34-0410-b5e6-96231b3b80d8
out of the AsmWriterEmitter. This patch does the physical
code movement, but leaves the implementation unchanged. I'll
make any changes necessary to generalize the code in a
separate patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95697 91177308-0d34-0410-b5e6-96231b3b80d8
for register tokens. Before, if it encountered
'%al,' it would report 'al,' as the token. Now it
correctly reports '%al'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95594 91177308-0d34-0410-b5e6-96231b3b80d8
disassembly library that provide access to
instruction information, and fixed ambiguous
wording in the comments for the header.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95274 91177308-0d34-0410-b5e6-96231b3b80d8
yesterday. This eliminates possible confusion
about what exactly in this directory; the name
is still short, though.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95118 91177308-0d34-0410-b5e6-96231b3b80d8
implementation. Also made sure that the register maps
were created during disassembler initialization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95051 91177308-0d34-0410-b5e6-96231b3b80d8
merely stubs out the blocks-based disassembly functions
if the library wasn't built with blocks, which allows a
constant .exports file and also properly deals with
situations in which the compiler used to build a client
is different from the compiler used to build the library.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95034 91177308-0d34-0410-b5e6-96231b3b80d8
fleshed out the .exports file. I still have to fix several
details of operand parsing, but the basic functionality is
there and usable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94974 91177308-0d34-0410-b5e6-96231b3b80d8
to the TargetAsmLexer class so that clients can
actually use the TargetAsmLexer they get from a
Target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94940 91177308-0d34-0410-b5e6-96231b3b80d8
library as a static and a shared library. Added dependencies
so the target-specific enhanced disassembly info tables are
built before the library.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94780 91177308-0d34-0410-b5e6-96231b3b80d8
TargetAsmLexer. Dialect-specific lexing code will
be placed in the functions LexTokenATT() and
LexTokenIntel().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94456 91177308-0d34-0410-b5e6-96231b3b80d8
be static. Also made it possible for clients to get it
and no other functions from ...GenAsmMatcher.inc by
defining REGISTERS_ONLY before including GenAsmMatcher.inc.
This sets the stage for target-specific lexers that can
identify registers and return AsmToken::Register as
appropriate.
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exactly like an MCAsmLexer. (The difference is that the
TargetAsmLexer knows how to handle target-specific stuff
like registers, whereas the MCAsmLexer is fully generic.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94237 91177308-0d34-0410-b5e6-96231b3b80d8
rather than passing them off to the AsmLexer to handle.
This means the AsmLexer no longer requires a SourceMgr
to do error handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94047 91177308-0d34-0410-b5e6-96231b3b80d8
the two token accessor functions are declared consistently.
Modified the clients of MCAsmParser to reflect this change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93916 91177308-0d34-0410-b5e6-96231b3b80d8
of include directives to occur within the parser itself.
This will break the lexer's dependency on a SourceMgr as
input.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93899 91177308-0d34-0410-b5e6-96231b3b80d8
Made LEA memory operands emit only 4 MCInst operands.
Made the scale operand equal 1 for instructions that have no
SIB byte.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91919 91177308-0d34-0410-b5e6-96231b3b80d8
incarnations), integrated into the MC framework.
The disassembler is table-driven, using a custom TableGen backend to
generate hierarchical tables optimized for fast decode. The disassembler
consumes MemoryObjects and produces arrays of MCInsts, adhering to the
abstract base class MCDisassembler (llvm/MC/MCDisassembler.h).
The disassembler is documented in detail in
- lib/Target/X86/Disassembler/X86Disassembler.cpp (disassembler runtime)
- utils/TableGen/DisassemblerEmitter.cpp (table emitter)
You can test the disassembler by running llvm-mc -disassemble for i386
or x86_64 targets. Please let me know if you encounter any problems
with it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91749 91177308-0d34-0410-b5e6-96231b3b80d8
with -disassemble, llvm-mc now accepts lines of the
form
0x00 0x00
and passes the resulting bytes to the disassembler for
the chosen (or default) target, printing the result.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91579 91177308-0d34-0410-b5e6-96231b3b80d8
Also fixed the corresponding testcase, and the PALIGNR
intrinsic (tested for correctness with llvm-gcc).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89491 91177308-0d34-0410-b5e6-96231b3b80d8
the Intel instruction tables.
The patterns will stay blank because ADD reg, reg
is faster, but having the encoding available is
useful for the disassembler.
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All of these do not have patterns (they're for the
disassembler).
Many of the floating-point instructions will probably
be rolled into definitions that have patterns, and may
eventually be superseded by mdefs. So I put them
together and left a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81979 91177308-0d34-0410-b5e6-96231b3b80d8
Intel tables, where the source operand is
specified by the R/M field and the destination
operand by the Reg field.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81914 91177308-0d34-0410-b5e6-96231b3b80d8
to the Intel register table.
Added 16- and 64-bit MOVs to and from the segment
registers to the Intel instruction tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81895 91177308-0d34-0410-b5e6-96231b3b80d8
Sean Callanan