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19979 Commits

Author SHA1 Message Date
Justin Holewinski
d3dec06447 PTX: Remove PTX calling convention files 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140377 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-23 14:18:27 +00:00
Justin Holewinski
1cde87d202 [PATCH 2/2] PTXInstrInfo.td PTXIntrinsicInstrInfo.td 80 columns 
From 5936c03172e251f12a0332d1033de5718e6e2091 Mon Sep 17 00:00:00 2001
---
 lib/Target/PTX/PTXInstrInfo.td          |  165 ++++++++++++++++++++----------
 lib/Target/PTX/PTXIntrinsicInstrInfo.td |   88 +++++++++++------
 2 files changed, 167 insertions(+), 86 deletions(-)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140376 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-23 14:18:24 +00:00
Justin Holewinski
27f08fc619 PTX: Generalize handling of .param types 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140375 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-23 14:18:22 +00:00
Justin Holewinski
04b5ebc74c PTX: Cleanup unused code in the PTXMFInfoExtract pass 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140374 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-23 14:18:19 +00:00
Akira Hatanaka
aaa9fc2e37 Add definitions of 64-bit int registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140366 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-23 02:33:15 +00:00
Akira Hatanaka
373e3a4091 Do not rely on the enum values of argument registers A0-A3 being consecutive. 
Define function getNextIntArgReg, which takes a register as a parameter and
returns the next O32 argument integer register. Use this function when double
precision floating point arguments are passed in two integer registers.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140363 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-23 00:58:33 +00:00
Eli Friedman
a6176adc8a PR10991: make fast-isel correctly check whether accessing a global through an alias involves thread-local storage. (I'm not entirely sure how this is supposed to work, but this patch makes fast-isel consistent with the normal isel path.) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140355 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 23:41:28 +00:00
Akira Hatanaka
40eda4626d Make changes in instruction and pattern definitions so that tablegen does not 
complain it cannot infer types in patterns. Fix a mistake in definition of 
SDT_MipsExtractElementF64.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140354 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 23:31:54 +00:00
Jakob Stoklund Olesen
4bd89873be Add support for GR32 <-> FR32 cross class copies. 
We already support GR64 <-> VR128 copies.  All of these copies break
partial register dependencies by zeroing the high part of the target
register.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140348 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 22:45:24 +00:00
Duncan Sands
17470bee5f Synthesize SSE3/AVX 128 bit horizontal add/sub instructions from 
floating point add/sub of appropriate shuffle vectors.  Does not
synthesize the 256 bit AVX versions because they work differently.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140332 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 20:15:48 +00:00
Akira Hatanaka
98f49c4413 Print parentheses in next line. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140325 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 18:29:29 +00:00
Akira Hatanaka
ebb90dbb54 Change subreg index of AFPR64 from sub_fpeven to sub_32 per Jakob's comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140324 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 18:24:21 +00:00
Akira Hatanaka
95a091a0b6 Define a new sub-register index sub_32 for accessing the 32-bit sub-register of 
a 64-bit integer register. Move the subreg index definitions to the beginning
of the file.





git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140319 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 17:57:32 +00:00
Akira Hatanaka
26bcc701a2 Print three closing parentheses when Kind is either VK_Mips_GPOFF_HI or 
VK_Mips_GPOFF_LO.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140316 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 17:44:37 +00:00
Akira Hatanaka
d27fda49c4 Add F31 to the set of callee-saved registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140315 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 17:35:03 +00:00
Akira Hatanaka
4e41416359 Fix typo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140313 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 17:26:58 +00:00
Justin Holewinski
7c9dd62441 PTX: Remove physical register defs 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140310 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 16:45:48 +00:00
Justin Holewinski
5422a0f166 PTX: Use .param space for device function return values on SM 2.0+, and attempt 
to fix up parameter passing on SM < 2.0

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140309 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 16:45:46 +00:00
Justin Holewinski
05591be5ed PTX: Fix style issues 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140308 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 16:45:43 +00:00
Justin Holewinski
297984d7c6 PTX: Fixup codegen to handle emission of virtual registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140307 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 16:45:40 +00:00
Justin Holewinski
40466cc758 PTX: Customize codegen passes in backend 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140306 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 16:45:37 +00:00
Justin Holewinski
247ee00bce PTX: Add new PTX-specific register allocator that keeps virtual registers 
instead of allocating physical registers.

This is part of a work-in-progress overhaul of the PTX register allocation scheme.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140305 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 16:45:33 +00:00
Craig Topper
adf01b3f18 Fix register printing in disassembling of push/pop of segment registers and in/out in Intel syntax mode. Fixes PR10960 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140299 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 07:01:50 +00:00
Akira Hatanaka
bb7d289aeb Add definition of 64-bit floating registers used for Mips64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140297 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 03:48:47 +00:00
Benjamin Kramer
2c2ccbf108 The SSE version differences for fmin/fmax are more involved than I thought. 
- x87: no min or max.
- SSE1: min/max for single precision scalars and vectors.
- SSE2: min/max for single and double precision scalars and vectors.
- AVX: as SSE2, but also supports the wider ymm vectors. (this is covered by the isTypeLegal check)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140296 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 03:27:22 +00:00
Akira Hatanaka
e33ca9ce1f Add enums and functions for symbols Mips64 uses. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140295 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 03:09:07 +00:00
Benjamin Kramer
74f3501d15 X86: Don't form min/max nodes if the target is missing SSE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140294 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 03:01:42 +00:00
Akira Hatanaka
459cad2dfd Mips64 aligns stack on 16-byte boundary. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140292 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 02:53:37 +00:00
Akira Hatanaka
c56f5ea4c3 Remove unnecessary condition check. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140291 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 02:41:29 +00:00
Owen Anderson
6126870193 Turns out that Thumb2 ADR doesn't need special printing like LDR does. Fix other test failures I caused. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140284 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-21 23:53:44 +00:00
Owen Anderson
e136872970 Print out immediate offset versions of PC-relative load/store instructions as [pc, #123] rather than simply #123. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140283 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-21 23:44:46 +00:00
Benjamin Kramer
15c9a1f60c X86Disassembler: if verbose logging is going to nulls(), disable logging completely. 
Otherwise we'll spend a ridiculous amount of time pretty printing debug output and then discarding it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140276 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-21 21:47:35 +00:00
Wesley Peck
91b60c1487 Fix some simple copy-paste errors in MBlaze ASM Parser and Makefile. 
patch contributed by Jia Liu!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140273 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-21 19:23:46 +00:00
Owen Anderson
519020adf1 These do not need to be conditional on the presence of CommentStream, as they have a fallback path now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140267 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-21 17:58:45 +00:00
Akira Hatanaka
0e64f810a5 Undo a change made in r140254. 
MipsArchVersion needs to be initialized to Mips32.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140261 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-21 17:31:45 +00:00
Nadav Rotem
64ac73bb15 fix comment 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140258 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-21 17:14:40 +00:00
Akira Hatanaka
47c40a2cf9 MipsArchVersion does not need to be in the initialization list and MipsABI 
should be initialized to UnknownABI.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140254 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-21 16:41:43 +00:00
Nadav Rotem
9c6cdf4c1c Insert a sanity check on the combining of x86 truncing-store nodes. This comes to replace the problematic check that was removed in r139995. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140246 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-21 08:45:10 +00:00
Richard Trieu
23946fcaae Change: 
assert(!"error message");

To:

  assert(0 && "error message");

which is more consistant across the code base.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140234 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-21 03:09:09 +00:00
Akira Hatanaka
2464810ac2 Add a base class for Mips TargetMachines and add Mips64 TargetMachines. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140233 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-21 03:00:58 +00:00
Akira Hatanaka
8c1b4bf066 Set ABI if it hasn't been set on the command line. 
Check if architecture & ABI combination is valid.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140230 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-21 02:45:29 +00:00
Akira Hatanaka
50fa74e8d2 Fix typo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140229 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-21 02:24:25 +00:00
Andrew Trick
3be654f808 Lower ARM adds/subs to add/sub after adding optional CPSR operand. 
This is still a hack until we can teach tblgen to generate the
optional CPSR operand rather than an implicit CPSR def. But the
strangeness is now limited to the selection DAG. ADD/SUB MI's no
longer have implicit CPSR defs, nor do we allow flag setting variants
of these opcodes in machine code. There are several corner cases to
consider, and getting one wrong would previously lead to nasty
miscompilation. It's not the first time I've debugged one, so this
time I added enough verification to ensure it won't happen again.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140228 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-21 02:20:46 +00:00
Andrew Trick
e23dc9c0ef whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140227 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-21 02:17:37 +00:00
Owen Anderson
317eaf1993 In the disassembler C API, be careful not to confuse the comment streamer that the disassembler outputs annotations on with the streamer that the InstPrinter will print them on. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140217 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-21 00:25:23 +00:00
Akira Hatanaka
5663344127 Change the names of functions isMips* to hasMips*. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140214 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-20 23:53:09 +00:00
Bruno Cardoso Lopes
f4b841d4e2 Revert r140097, working on a better approach 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140203 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-20 23:19:29 +00:00
Bruno Cardoso Lopes
149f29f1fd Simplify max/minp[s|d] dagcombine matching 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140199 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-20 22:34:45 +00:00
Bruno Cardoso Lopes
4e42335972 Tidy up a bit more, fix tab and remove trailing whitespaces 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140186 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-20 21:45:26 +00:00
Bruno Cardoso Lopes
448d986858 The wrong relocation was being emitted for several SSSE3 instructions. 
This fixes PR10963. Thanks to Benjamin for finding the wrong tablegen
declaration.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140184 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-20 21:39:21 +00:00