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87 Commits

Author SHA1 Message Date
Vincent Lejeune
acf7350385 R600: Remove predicated_break inst 
We were using two instructions for similar purpose : break and
predicated break. Only predicated_break was emitted and it was
lowered at R600ControlFlowFinalizer to JUMP;CF_BREAK;POP.
This commit simplify the situation by making AMDILCFGStructurizer
emit IF_PREDICATE;BREAK;ENDIF; instead of predicated_break (which
is now removed).

There is no functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187510 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-31 19:31:14 +00:00
Tom Stellard
8ea83d4999 R600: Treat CONSTANT_ADDRESS loads like GLOBAL_ADDRESS loads when necessary 
These are really the same address space in hardware.  The only
difference is that CONSTANT_ADDRESS uses a special cache for faster
access.  When we are unable to use the constant kcache for some reason
(e.g. smaller types or lack of indirect addressing) then the instruction
selector must use GLOBAL_ADDRESS loads instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187006 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-23 23:54:56 +00:00
Tom Stellard
10205d5a73 R600: Add support for 24-bit MAD instructions 
Reviewed-by: Vincent Lejeune <vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186923 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-23 01:48:49 +00:00
Tom Stellard
3f5d63b956 R600: Add support for 24-bit MUL instructions 
Reviewed-by: Vincent Lejeune <vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186922 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-23 01:48:42 +00:00
Tom Stellard
eb643b9b37 R600: Improve support for < 32-bit loads 
Reviewed-by: Vincent Lejeune <vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186921 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-23 01:48:35 +00:00
Tom Stellard
a7eea0568c R600: Use KCache for kernel arguments 
Reviewed-by: Vincent Lejeune <vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186918 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-23 01:48:18 +00:00
Tom Stellard
2bb20fd2bf R600: Clean up extended load patterns 
Reviewed-by: Vincent Lejeune <vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186914 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-23 01:47:52 +00:00
Vincent Lejeune
272458bd06 R600: Don't emit empty then clause and use alu_pop_after 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186725 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-19 21:45:15 +00:00
Vincent Lejeune
f2cfef8172 R600: Do not predicated basic block with multiple alu clause 
Test is not included as it is several 1000 lines long.
To test this functionnality, a test case must generate at least 2 ALU clauses,
where an ALU clause is ~110 instructions long.

NOTE: This is a candidate for the stable branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185943 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-09 15:03:33 +00:00
Vincent Lejeune
c6f13db656 R600: Use DAG lowering pass to handle fcos/fsin 
NOTE: This is a candidate for the stable branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185940 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-09 15:03:11 +00:00
Vincent Lejeune
f79b9b8593 R600: Print Export Swizzle 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185939 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-09 15:03:03 +00:00
Vincent Lejeune
8f9fbd67c3 R600: Support schedule and packetization of trans-only inst 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185268 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-29 19:32:43 +00:00
Tom Stellard
e3d4cbc7d2 R600: Add local memory support via LDS 
Reviewed-by: Vincent Lejeune<vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185162 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-28 15:47:08 +00:00
Tom Stellard
cedcfee405 R600: Add support for GROUP_BARRIER instruction 
Reviewed-by: Vincent Lejeune<vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185161 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-28 15:46:59 +00:00
Tom Stellard
7e9381951e R600: Add ALUInst bit to tablegen definitions v2 
v2:
  - Remove functions left over from a previous rebase.

Reviewed-by: Vincent Lejeune<vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185160 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-28 15:46:53 +00:00
Tom Stellard
5e48a0e9ae R600: Use new getNamedOperandIdx function generated by TableGen 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184880 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-25 21:22:18 +00:00
Tom Stellard
d67d029b6d R600: Add support for i32 loads from the constant address space on Cayman 
Tested-By: Aaron Watry <awatry@gmail.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184821 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-25 02:39:30 +00:00
Aaron Watry
6c4b8fe9dd R600: Fix spelling error in comment 
our -> or

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184756 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-24 16:57:57 +00:00
Vincent Lejeune
98f5cf8000 R600: Properly set COUNT_3 bit in TEX clause initiating inst for pre EG gen. 
Fixes rv7x0 bug in Heaven reported here:
https://bugs.freedesktop.org/show_bug.cgi?id=64257

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184116 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-17 20:16:26 +00:00
Tom Stellard
d6055262d2 R600: Use correct encoding for Vertex Fetch instructions on Cayman 
Reviewed-by: Vincent Lejeune<vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184016 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-14 22:12:30 +00:00
Tom Stellard
4efccd0fb1 R600: Use EXPORT_RAT_INST_STORE_DWORD for stores on Cayman 
We were using RAT_INST_STORE_RAW, which seemed to work, but the docs
say this instruction doesn't exist for Cayman, so it's probably safer
to use a documented instruction instead.

Reviewed-by: Vincent Lejeune<vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184015 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-14 22:12:24 +00:00
Tom Stellard
c30b232349 R600: Factor the instruction encoding out the RAT_WRITE_CACHELESS_eg class 
Reviewed-by: Vincent Lejeune<vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184014 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-14 22:12:19 +00:00
Tom Stellard
2def95fc1e R600: Move instruction encoding definitions into a separate .td file 
Reviewed-by: Vincent Lejeune<vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184013 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-14 22:12:09 +00:00
Tom Stellard
3ff0abfaab R600: Rework subtarget info and remove AMDILDevice classes 
This should simplify the subtarget definitions and make it easier to
add new ones.

Reviewed-by: Vincent Lejeune <vljn@ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183566 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 20:37:48 +00:00
Vincent Lejeune
0962e147a4 R600: Constraints input regs of interp_xy,_zw 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183106 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-03 15:44:16 +00:00
Tom Stellard
ba534c2143 R600: Swap the legality of rotl and rotr 
The hardware supports rotr and not rotl.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182285 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-20 15:02:19 +00:00
Vincent Lejeune
4ed9917147 R600: Relax some vector constraints on Dot4. 
Dot4 now uses 8 scalar operands instead of 2 vectors one which allows register
coalescer to remove some unneeded COPY.
This patch also defines some structures/functions that can be used to handle
every vector instructions (CUBE, Cayman special instructions...) in a similar
fashion.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182126 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-17 16:50:32 +00:00
Vincent Lejeune
d3293b49f9 R600: Improve texture handling 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182125 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-17 16:50:20 +00:00
Vincent Lejeune
4109bd8829 R600: Rename 128 bit registers. 
Almost all instructions that takes a 128 bits reg as input (fetch, export...)
have the abilities to swizzle their argument and output. Instead of printing
default swizzle for each 128 bits reg, rename T*.XYZW to T* and let instructions
print potentially optimized swizzles themselves.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182124 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-17 16:50:09 +00:00
Vincent Lejeune
9a9e936650 R600: prettier dump of clamp 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182121 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-17 16:49:49 +00:00
Tom Stellard
58e87a68a8 R600: Remove AMDILPeeopholeOptimizer and replace optimizations with tablegen patterns 
The BFE optimization was the only one we were actually using, and it was
emitting an intrinsic that we don't support.

https://bugs.freedesktop.org/show_bug.cgi?id=64201

Reviewed-by: Christian König <christian.koenig@amd.com>

NOTE: This is a candidate for the 3.3 branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181580 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-10 02:09:45 +00:00
Tom Stellard
8b1c60c151 R600: BFI_INT is a vector-only instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181034 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-03 17:21:24 +00:00
Tom Stellard
83f0a5a5e8 R600: Add pattern for SHA-256 Ma function 
This can be optimized using the BFI_INT instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181033 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-03 17:21:20 +00:00
Vincent Lejeune
9e1808733e R600: Improve asmPrint of ALU clause 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180957 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-02 21:52:40 +00:00
Vincent Lejeune
92f24d403f R600: Prettier asmPrint of Alu 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180956 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-02 21:52:30 +00:00
Tom Stellard
399880527d R600: Use new tablegen syntax for patterns 
All but two patterns have been converted to the new syntax.  The
remaining two patterns will require COPY_TO_REGCLASS instructions, which
the VLIW DAG Scheduler cannot handle.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180922 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-02 15:30:12 +00:00
Vincent Lejeune
2c836f84db R600: use native for alu 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180761 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-30 00:14:38 +00:00
Vincent Lejeune
abcde265b1 R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chips 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180759 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-30 00:14:17 +00:00
Vincent Lejeune
e332e3559b R600: Add a Bank Swizzle operand 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180758 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-30 00:14:08 +00:00
Vincent Lejeune
b6379de427 R600: Turn TEX/VTX into native instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180756 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-30 00:13:53 +00:00
Vincent Lejeune
631591e6f3 R600: Add FetchInst bit to instruction defs to denote vertex/tex instructions 
v2[Vincent Lejeune]: Split FetchInst into usesTextureCache/usesVertexCache

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180755 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-30 00:13:39 +00:00
Vincent Lejeune
8723c9ebf5 R600: Clean up instruction class definitions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180752 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-30 00:13:20 +00:00
Tom Stellard
015f586bc9 R600: Fix encoding of CF_END_{EG, R600} instructions 
The EOP bit was not being encoded.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180734 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-29 22:23:54 +00:00
Vincent Lejeune
2a74639bc7 R600: Use .AMDGPU.config section to emit stacksize 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180124 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-23 17:34:12 +00:00
Vincent Lejeune
7a28d8afa7 R600: Add CF_END 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180123 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-23 17:34:00 +00:00
Tom Stellard
48b809e6e5 R600: Add pattern for the BFI_INT instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179830 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-19 02:11:06 +00:00
Vincent Lejeune
26ebd7aafc R600: Make Export Instruction not duplicable 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179686 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-17 15:17:39 +00:00
Vincent Lejeune
58df169e82 R600: Export is emitted as a CF_NATIVE inst 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179685 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-17 15:17:32 +00:00
Michel Danzer
b187f8cd1c R600/SI: Add pattern for AMDGPUurecip 
21 more little piglits with radeonsi.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179186 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-10 17:17:56 +00:00
Vincent Lejeune
bd7c634ab9 R600: Control Flow support for pre EG gen 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179020 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-08 13:05:49 +00:00