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459 Commits

Author SHA1 Message Date
Jozef Kolek
ad017096fc [mips][microMIPS] Implement BEQZ16 and BNEZ16 instructions 
Differential Revision: http://reviews.llvm.org/D5271


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225627 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-12 12:03:34 +00:00
Zoran Jovanovic
25547ee83c [mips][microMIPS] Relocate with symbol for micromips symbols 
Differential Revision: http://reviews.llvm.org/D6796


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225008 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-30 22:04:16 +00:00
Jozef Kolek
c623d0af3d [mips][microMIPS] Implement CACHE, PREF, SSNOP, EHB and PAUSE instructions 
Differential Revision: http://reviews.llvm.org/D5204


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224785 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-23 19:55:34 +00:00
Jozef Kolek
e5fa612e9e [mips][microMIPS] Implement LWSP and SWSP instructions 
Differential Revision: http://reviews.llvm.org/D6416


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224771 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-23 16:16:33 +00:00
Zoran Jovanovic
78f6aad800 [mips][microMIPS] Implement SWP and LWP instructions 
Differential Revision: http://reviews.llvm.org/D5667


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224338 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-16 14:59:10 +00:00
Vladimir Medic
462763dc0b The andi16, addiusp and jraddiusp micromips instructions were missing dedicated decoder methods in MipsDisassembler.cpp to properly decode immediate operands. These methods are added together with corresponding tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223006 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-01 11:12:04 +00:00
Jozef Kolek
b087448a5f [mips][microMIPS] Implement NOP aliases 
This patch implements microMIPS 16-bit (MOVE16 $0, $0) and
32-bit (SLL $0, $0, 0) NOP aliases.

http://reviews.llvm.org/D6440


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222953 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-29 13:29:24 +00:00
Zoran Jovanovic
7dc6143a82 [mips][microMIPS] Implement SWM16 and LWM16 instructions 
Differential Revision: http://reviews.llvm.org/D5579


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222901 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-27 18:28:59 +00:00
Jozef Kolek
13fbabb7c8 [mips][microMIPS] Implement BREAK16 and SDBBP16 instructions 
Patch by Radovan Obradovic.

Differential Revision: http://reviews.llvm.org/D5048


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222900 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-27 18:18:42 +00:00
Daniel Sanders
68de93c3b4 [mips] Add synci instruction. 
Patch by Amaury Pouly

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D6421


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222899 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-27 17:28:10 +00:00
Jozef Kolek
832e2301cd [mips][microMIPS] Implement disassembler support for 16-bit instructions LBU16, LHU16, LW16, SB16, SH16 and SW16 
Differential Revision: http://reviews.llvm.org/D6405


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222847 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-26 18:56:38 +00:00
Jozef Kolek
c19526770e [mips][microMIPS] Fix JRADDIUSP instruction 
Fix JRADDIUSP instruction, remove delay slot flag because this instruction
doesn't have delay slot.

Differential Revision: http://reviews.llvm.org/D6365


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222658 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-24 16:14:10 +00:00
Jozef Kolek
b955bed064 [mips][microMIPS] Implement LBU16, LHU16, LW16, SB16, SH16 and SW16 instructions 
Differential Revision: http://reviews.llvm.org/D5122


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222653 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-24 14:39:13 +00:00
Zoran Jovanovic
d67cd80220 [mips][micromips] Implement SWM32 and LWM32 instructions 
Differential Revision: http://reviews.llvm.org/D5519


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222367 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-19 16:44:02 +00:00
Jozef Kolek
9fece51399 [mips][microMIPS] Fix opcodes of MFHC1 and MTHC1 instructions. 
Differential Revision: http://reviews.llvm.org/D6169


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222355 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-19 13:37:51 +00:00
Jozef Kolek
43ae00e4e0 [mips][microMIPS] Implement LWXS instruction. 
Differential Revision: http://reviews.llvm.org/D5407


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222348 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-19 11:39:12 +00:00
Jozef Kolek
baf97d8987 [mips][microMIPS] Implement SDBBP and RDHWR instructions. 
Differential Revision: http://reviews.llvm.org/D5240


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222347 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-19 11:25:50 +00:00
Vasileios Kalintiris
b001cb6423 [mips] Add hardware register name "hwr_ulr" ($29) 
The canonical name when printing assembly is still $29. The reason is that
GAS does not accept "$hwr_ulr" at the moment.

This addresses the comments from r221307, which reverted the original
commit r221299.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221685 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-11 11:22:39 +00:00
Vasileios Kalintiris
d3da72c5b3 Recommit "[mips] Add names and tests for the hardware registers" 
The original commit r221299 was reverted in r221307.  I removed the name
"hrw_ulr" ($29) from the original commit because two tests were failing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221681 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-11 10:31:31 +00:00
David Majnemer
1dd631fe02 llvm-objdump: Skip empty sections when dumping contents 
Empty sections are just noise when using objdump.
This is similar to what binutils does.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221680 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-11 09:58:25 +00:00
Toma Tabacu
ea60f51d87 [mips] Improve error/warning messages and testing for the .cpload assembler directive. 
Summary:
Improved warning message when using .cpload inside a reorder section and added an error message for using .cpload with Mips16 enabled.
Modified the tests to fit with the changes mentioned above, added a test-case for the N32 ABI in cpload.s and did some reformatting to make the tests easier to read.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D5465

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221447 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-06 10:02:45 +00:00
Zoran Jovanovic
8dad1e1e8e [mips][microMIPS] Implement ANDI16 instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221367 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-05 17:31:00 +00:00
Zoran Jovanovic
0f0a134d9d [mips][microMIPS] Mark symbols as microMIPS if necessary 
Differential Revision: http://reviews.llvm.org/D6039


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221355 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-05 16:35:20 +00:00
Zoran Jovanovic
e9b9ca452f Reverted revisions 221351, 221352 and 221353. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221354 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-05 16:19:59 +00:00
Zoran Jovanovic
7c63a6331f [mips][microMIPS] Implement ANDI16 instruction 
Differential Revision: http://reviews.llvm.org/D5163


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221351 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-05 15:39:41 +00:00
Rafael Espindola
2ca0328c3b Revert "[mips] Add names and tests for the hardware registers" 
This reverts commit r221299.

The tests

    LLVM :: MC/Disassembler/Mips/mips32.txt
    LLVM :: MC/Disassembler/Mips/mips32_le.txt

were failing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221307 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-04 22:15:05 +00:00
Vasileios Kalintiris
a7a01d3c98 [mips] Add names and tests for the hardware registers 
Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D5763

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221299 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-04 21:30:44 +00:00
Toma Tabacu
dd3894aa8f [mips] Improve support for the .set mips16/nomips16 assembler directives. 
Summary:
Appropriately set/clear the FeatureBit for Mips16 when these assembler directives are used and also emit ".set nomips16" (previously, only ".set mips16" was being emitted).

These improvements allow for better testing of the .cpload/.cprestore assembler directives (which are not supposed to work when Mips16 is enabled).

Test Plan: The test is bare-bones because there are no MC tests for Mips16 instructions (there's only one, which checks that the Mips16 ELF header flag gets set), and that suggests to me that it has not been implemented yet in the IAS.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D5462

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221277 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-04 17:18:07 +00:00
Zoran Jovanovic
71832e7ed9 [mips][microMIPS] Implement ADDIUR1SP instruction 
Differential Revision: http://reviews.llvm.org/D5153


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220477 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-23 11:13:59 +00:00
Zoran Jovanovic
fd515137bc ps][microMIPS] Implement ADDIUR2 instruction 
Differential Revision: http://reviews.llvm.org/D5151


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220476 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-23 11:06:34 +00:00
Zoran Jovanovic
f58c95aac0 ps][microMIPS] Implement LI16 instruction 
Differential Revision: http://reviews.llvm.org/D5149


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220475 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-23 10:59:24 +00:00
Zoran Jovanovic
558236adf0 [mips][microMIPS] Implement CodeGen support for SLL16 and SRL16 instructions 
Differential Revision: http://reviews.llvm.org/D5774


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220474 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-23 10:42:01 +00:00
Derek Schuff
5385df6bba Fix Mips nacl-mask test for new bundle-aligned label behavior 
After r220439 the behavior of labels in bundle-align mode changed,
and I neglected to update this test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220447 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-22 23:32:00 +00:00
Zoran Jovanovic
59e16813d2 [mips][microMIPS] Implement ADDU16 and SUBU16 instructions 
Differential Revision: http://reviews.llvm.org/D5118


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220276 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-21 08:44:58 +00:00
Zoran Jovanovic
a245b68293 [mips][microMIPS] Implement AND16, NOT16, OR16 and XOR16 instructions 
Differential Revision: http://reviews.llvm.org/D5117


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220275 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-21 08:32:40 +00:00
Vasileios Kalintiris
eaf8f5efe9 [mips] Add support for COP1's Branch-On-Cond-Likely instructions 
Summary: Depends on D5782

Reviewers: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D5802

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220042 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-17 14:08:28 +00:00
Vasileios Kalintiris
0f22fe9b56 [mips] Add support for COP0's Branch-On-Cond-Likely instructions 
Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D5782

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220036 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-17 12:38:35 +00:00
Vasileios Kalintiris
02065a65cd [mips] Marked the DI/EI instruction aliases as MIPS32r2 
Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D5751

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219927 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-16 15:23:52 +00:00
Zoran Jovanovic
0bf4807a90 [mips][microMIPS] Implement ADDIUSP instruction 
Differential Revision: http://reviews.llvm.org/D5084


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219500 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-10 14:37:30 +00:00
Zoran Jovanovic
24335e60c7 [mips][microMIPS] Implement JR16 instruction 
Differential Revision: http://reviews.llvm.org/D5062


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219498 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-10 14:02:44 +00:00
Zoran Jovanovic
e2db3024be [mips][microMIPS] Implement ADDIUS5 instruction 
Differential Revision: http://reviews.llvm.org/D5049


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219495 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-10 13:45:34 +00:00
Zoran Jovanovic
28b2826538 ps][microMIPS] Implement JRC instruction 
Differential Revision: http://reviews.llvm.org/D5045


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219494 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-10 13:31:18 +00:00
Zoran Jovanovic
b581230077 [mips][microMIPS] Implement JALRS16 instruction 
Differential Revision: http://reviews.llvm.org/D5027


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219493 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-10 13:22:28 +00:00
Daniel Sanders
61bc405795 [mips] Print warning when using register names not available in N32/64 
Summary:
The register names t4-t7 are not available in the N32 and N64 ABIs.
This patch prints a warning, when those names are used in N32/64,
along with a fix-it with the correct register names.

Patch by Vasileios Kalintiris

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D5272


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218989 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-03 15:37:37 +00:00
Joerg Sonnenberger
92583e0712 Support padding unaligned data in .text. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218870 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-02 13:41:42 +00:00
Toma Tabacu
4378ff024d [mips] Add assembler support for the .set nodsp directive. 
Summary: This directive is used to tell the assembler to reject DSP-specific instructions.

Reviewers: dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D5142

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217946 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-09-17 09:01:54 +00:00
Toma Tabacu
cdb6326c1f [mips] Improve the error messages given by MipsAsmParser. 
Summary: Changed error messages to be more informative and to resemble other clang/llvm error messages (first letter is lower case, no ending punctuation) and updated corresponding tests.

Reviewers: dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D5065

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217873 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-09-16 15:00:52 +00:00
Toma Tabacu
e40de571ad [mips] Move 32-bit ADDiu instruction alias from Mips64InstrInfo.td to MipsInstrInfo.td. 
Patch by Vasileios Kalintiris.

Differential Revision: http://reviews.llvm.org/D5244



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217868 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-09-16 10:19:03 +00:00
Toma Tabacu
c6380f0b05 [mips] Marked the ADDi instruction aliases as not available in Mips32R6 and Mips64R6. 
Patch by Vasileios Kalintiris.

Differential Revision: http://reviews.llvm.org/D5242



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217867 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-09-16 09:26:09 +00:00
Toma Tabacu
fcc1a51d3d [mips] Marked the DADDiu instruction aliases as MIPS III. 
Patch by Vasileios Kalintiris.

Differential Revision: http://reviews.llvm.org/D5239



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217770 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-09-15 14:47:46 +00:00