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1027 Commits

Author SHA1 Message Date
Evan Cheng
c59420867e Give ARMISD::EH_SJLJ_LONGJMP and EH_SJLJ_SETJMP names. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85381 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-28 06:55:03 +00:00
Evan Cheng
39382427f1 Use fconsts and fconstd to materialize small fp constants. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85362 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-28 01:44:26 +00:00
Bob Wilson
20d108140e Most of the NEON shuffle instructions do not support 64-bit element types. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84785 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 21:36:27 +00:00
Evan Cheng
2095659a85 Match more patterns to movt. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84751 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 08:15:52 +00:00
Benjamin Kramer
174101e13a Random #include pruning. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84632 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-20 11:44:38 +00:00
Bob Wilson
934f98b536 Revert svn r80498 and replace it with a different solution. The only problem 
I can see with the original code was that I forgot that this runs after
type legalization and hence the result type will always be i32. (Custom
legalization of EXTRACT_VECTOR_ELT is only enabled for vector types with
8- and 16-bit elements.)

Regarding the FIXME comment: any information about sign and zero-extension
should be captured by separate extension operations.  The DAG combiner should
handle those to produce either VGETLANEu or VGETLANEs, and that seems to be
working now.  If there are cases that we're missing, let me know.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84218 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-15 23:12:05 +00:00
Bob Wilson
e72142aa5b More Neon clean-up: avoid the need for custom-lowering vld/st-lane intrinsics 
by creating TargetConstants during instruction selection instead of during
legalization.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84042 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-13 22:29:24 +00:00
Bob Wilson
73d64a6fd3 NEON VLD/VST are now fully implemented. For operations that expand to 
multiple instructions, the expansion is done during selection so there is
no need to do anything special during legalization.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84036 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-13 21:55:24 +00:00
Anton Korobeynikov
249fb339ad Add PseudoSourceValues for constpool stuff on ELF (Darwin should use something similar) 
and register spills.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83435 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 00:06:35 +00:00
Evan Cheng
048e36f536 getFunctionAlignment should return log2 alignment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83242 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-02 06:57:25 +00:00
Anton Korobeynikov
48e1935284 ARM does not support offset folding (yet). Disable it for now. 
This fixes PR5031. Unfortunately, there is no small testcase :(

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82643 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-23 19:04:09 +00:00
Evan Cheng
ce31910eae Fix PR4926. When target hook EmitInstrWithCustomInserter() insert new basic blocks and update CFG, it should also inform sdisel of the changes so the phi source operands will come from the right basic blocks. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82311 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-19 09:51:03 +00:00
Evan Cheng
fb2e752e41 Enhance EmitInstrWithCustomInserter() so target can specify CFG changes that sdisel will use to properly complete phi nodes. 
Not functionality change yet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82273 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-18 21:02:19 +00:00
Bob Wilson
0696fdf322 Expand vector floating-point conversions not supported by NEON. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82074 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-16 20:20:44 +00:00
Bob Wilson
642b329104 Expand some more vector operations not supported by Neon. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81969 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-16 00:32:15 +00:00
Bob Wilson
1633076c47 Neon does not support vector divide or remainder. Expand them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81966 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-16 00:17:28 +00:00
Bob Wilson
74dc72e89b Expand all v2f64 arithmetic operations for Neon. 
Radar 7200803.  (This should also fix the
SingleSource/UnitTests/Vector/sumarray-dbl test.)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81959 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-15 23:55:57 +00:00
Bob Wilson
cd3b9a4f17 Fix pr4939: Change FPCCToARMCC to translate SETOLE to ARMCC::LS. 
See the bug report for details.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81397 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-09 23:14:54 +00:00
Anton Korobeynikov
2ba62ef7f2 Unbreak getOnesVector() / getZeroVector() to use valid ARM extended imm's. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81262 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-08 22:51:43 +00:00
Evan Cheng
63476a8040 Reference to hidden symbols do not have to go through non-lazy pointer in non-pic mode. rdar://7187172. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80904 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-03 07:04:02 +00:00
Sandeep Patel
65c3c8f323 Retype from unsigned to CallingConv::ID accordingly. Approved by Bob Wilson. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80773 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-02 08:44:58 +00:00
Bob Wilson
8a3198b770 Add support for generating code for vst{234}lane intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80707 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-01 18:51:56 +00:00
Bob Wilson
243fcc5a69 Generate code for vld{234}_lane intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80656 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-01 04:26:28 +00:00
Jim Grosbach
3fb2b1ede3 Clean up LSDA name generation and use for SJLJ exception handling. This 
makes an eggregious hack somewhat more palatable. Bringing the LSDA forward
and making it a GV available for reference would be even better, but is
beyond the scope of what I'm looking to solve at this point.

Objective C++ code could generate function names that broke the previous
scheme. This fixes that.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80649 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-01 01:57:56 +00:00
Anton Korobeynikov
b00c03bb35 EXTRACT_VECTOR_ELEMENT can have result type different from element type. 
Remove the assertion and generalize the code for ARM NEON stuff.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80498 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-30 17:14:54 +00:00
Anton Korobeynikov
71624cc786 Do not assert on too wide splats we don't support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80409 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-29 00:08:18 +00:00
Evan Cheng
e4e4ed3b56 Let Darwin linker auto-synthesize stubs and lazy-pointers. This deletes a bunch of nasty code in ARM asm printer. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80404 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-28 23:18:09 +00:00
Anton Korobeynikov
b5fb4282cd Hopefully the final missing part :( 
scalar_to_vector is fully legal now

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80251 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-27 16:25:49 +00:00
Anton Korobeynikov
fdf189ac97 Transform float scalar_to_vector into subreg accesses. 
No idea whether this is profitable or not.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80245 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-27 14:38:44 +00:00
Bob Wilson
31fb12f93a Remove unneeded ARM-specific DAG nodes for VLD* and VST* Neon operations. 
The instructions can be selected directly from the intrinsics.  We will need
to add some ARM-specific nodes for VLD/VST of 3 and 4 128-bit vectors, but
those are not yet implemented.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80117 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-26 17:39:53 +00:00
Anton Korobeynikov
1cb852b0ea Expand scalar_to_vector - we don't have any isel logic for it now 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80107 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-26 16:26:09 +00:00
Eli Friedman
ce392eb3ea Make x86 test actually test x86 code generation. Fix the 
construct on ARM, which was breaking by coincidence, and add a similar 
testcase for ARM.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79719 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-22 03:13:10 +00:00
Bob Wilson
c692cb77aa Match VTRN, VZIP, and VUZP shuffles. Restore the tests for these operations, 
now using shuffles instead of intrinsics.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79673 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-21 20:54:19 +00:00
Anton Korobeynikov
051cfd683f Fix some typos and use type-based isel for VZIP/VUZP/VTRN 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79625 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-21 12:41:42 +00:00
Anton Korobeynikov
1c8e581832 Add lowering of ARM 4-element shuffles to multiple instructios via perfectshuffle-generated table. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79624 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-21 12:41:24 +00:00
Anton Korobeynikov
62e84f177d Add nodes & dummy matchers for some v{zip,uzp,trn} instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79622 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-21 12:40:50 +00:00
Anton Korobeynikov
8e6c2b9041 Expand EXTRACT_SUBVECTOR 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79621 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-21 12:40:35 +00:00
Anton Korobeynikov
5da894f5c4 Provide vext.{16,32} 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79620 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-21 12:40:21 +00:00
Anton Korobeynikov
d0ac234b1b Use masks not nodes for vector shuffle predicates. Provide set of 'legal' masks, so legalizer won't infinite cycle 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79619 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-21 12:40:07 +00:00
Bob Wilson
de95c1b88b Add support for Neon VEXT (vector extract) shuffles. 
This is derived from a patch by Anton Korzh.  I modified it to recognize
the VEXT shuffles during legalization and lower them to a target-specific
DAG node.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79428 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-19 17:03:43 +00:00
Bill Wendling
af56634058 Reapply r79127. It was fixed by d0k. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79136 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-15 21:21:19 +00:00
Bill Wendling
f865ea85bd Revert r79127. It was causing compilation errors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79135 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-15 21:14:01 +00:00
Evan Cheng
088880cb19 Change allowsUnalignedMemoryAccesses to take type argument since some targets 
support unaligned mem access only for certain types. (Should it be size
instead?)

ARM v7 supports unaligned access for i16 and i32, some v6 variants support it
as well.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79127 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-15 19:23:44 +00:00
Evan Cheng
bc9b754091 Turn on if-conversion for thumb2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79084 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-15 07:59:10 +00:00
Anton Korobeynikov
72977a45a8 Allow targets to specify their choice of calling conventions per 
libcall. Take advantage of this in the ARM backend to rectify broken
choice of CC when hard float is in effect. PIC16 may want to see if
it could be of use in MakePIC16Libcall, which works unchanged.

Patch by Sandeep!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79033 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-14 20:10:52 +00:00
Evan Cheng
e6c835f424 Add Thumb2 lsr hooks. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79032 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-14 20:09:37 +00:00
Evan Cheng
59bc0604e5 80 col violation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79026 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-14 19:11:20 +00:00
Bob Wilson
22cac0d9b3 Now that all the legal Neon shuffles (or at least the ones that have been 
implemented so far) are recognized during legalization, it is easy to fall
back to the default expansion for other shuffles.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78995 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-14 05:16:33 +00:00
Bob Wilson
c1d287b4b7 Create a new ARM-specific DAG node, VDUP, to represent a splat from a 
scalar_to_vector.  Generate these VDUP nodes during legalization instead
of trying to recognize the pattern during selection.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78994 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-14 05:13:08 +00:00
Bob Wilson
0ce3710825 During legalization, change Neon vdup_lane operations from shuffles to 
target-specific VDUPLANE nodes.  This allows the subreg handling for the
quad-register version to be done easily with Pats in the .td file, instead
of with custom code in ARMISelDAGToDAG.cpp.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78993 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-14 05:08:32 +00:00