5 Commits

Author SHA1 Message Date
Tom Stellard
3ff0abfaab R600: Rework subtarget info and remove AMDILDevice classes
This should simplify the subtarget definitions and make it easier to
add new ones.

Reviewed-by: Vincent Lejeune <vljn@ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183566 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-07 20:37:48 +00:00
Vincent Lejeune
dcfcf1d1ff R600: Factorize Fetch size limit inside AMDGPUSubTarget
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182122 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-17 16:49:55 +00:00
Vincent Lejeune
631591e6f3 R600: Add FetchInst bit to instruction defs to denote vertex/tex instructions
v2[Vincent Lejeune]: Split FetchInst into usesTextureCache/usesVertexCache

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180755 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30 00:13:39 +00:00
Dmitri Gribenko
96f498bd9f Remove redundant 'llvm::' qualifications
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172358 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-13 16:01:15 +00:00
Tom Stellard
f98f2ce29e Add R600 backend
A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169915 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11 21:25:42 +00:00