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170 Commits

Author SHA1 Message Date
Evan Cheng
b093bd0565 Fix what looks to me obvious instruction definition bugs. 
1. CMPXCHG8B and CMPXCHG16B did not specify implicit physical register defs and uses.
2. LCMPXCHG8B is loading 64 bit memory, not 32 bit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92985 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-08 01:29:19 +00:00
Evan Cheng
760d1945bc Perform this folding as a target specific dag combine: 
(or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)

The isel patterns may not catch all the cases if general dag combine has reduced width of source operands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92513 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-04 21:22:48 +00:00
Sean Callanan
108934c65d Instruction fixes, added instructions, and AsmString changes in the 
X86 instruction tables.

Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.

This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.

* X86*.td
	Removed tabs and fixed 80-line violations

* X86Instr64bit.td
	(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
		Added
	(CALL, CMOV) Added qualifiers
	(JMP) Added PC-relative jump instruction
	(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
		that it is 64-bit only (ambiguous since it has no
		REX prefix)
	(MOV) Added rr form going the other way, which is encoded
		differently
	(MOV) Changed immediates to offsets, which is more correct;
		also fixed MOV64o64a to have to a 64-bit offset
	(MOV) Fixed qualifiers
	(MOV) Added debug-register and condition-register moves
	(MOVZX) Added more forms
	(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
		(as with MOV) are encoded differently
	(ROL) Made REX.W required
	(BT) Uncommented mr form for disassembly only
	(CVT__2__) Added several missing non-intrinsic forms
	(LXADD, XCHG) Reordered operands to make more sense for
		MRMSrcMem
	(XCHG) Added register-to-register forms
	(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
	(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
		Added
* X86InstrFPStack.td
	(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
	 FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
	 FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
	 FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
	 FXRSTOR)
		Added
	(FCOM, FCOMP) Added qualifiers
	(FSTENV, FSAVE, FSTSW) Fixed opcode names
	(FNSTSW) Added implicit register operand
* X86InstrInfo.td
	(opaque512mem) Added for FXSAVE/FXRSTOR
	(offset8, offset16, offset32, offset64) Added for MOV
	(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
	 LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
	 LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
	 LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
	 CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
	 SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
	 VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
	 VMWRITE, VMXOFF, VMXON) Added
	(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
	(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
	 JGE, JLE, JG, JCXZ) Added 32-bit forms
	(MOV) Changed some immediate forms to offset forms
	(MOV) Added reversed reg-reg forms, which are encoded
		differently
	(MOV) Added debug-register and condition-register moves
	(CMOV) Added qualifiers
	(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
	(BT) Uncommented memory-register forms for disassembler
	(MOVSX, MOVZX) Added forms
	(XCHG, LXADD) Made operand order make sense for MRMSrcMem
	(XCHG) Added register-register forms
	(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
	(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
	change

* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
  qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91638 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-18 00:01:26 +00:00
Evan Cheng
2e489c4f9d Re-enable 91381 with fixes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91489 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-16 00:53:11 +00:00
Evan Cheng
dba6cac0d4 Fix an encoding bug. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91417 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-15 06:49:02 +00:00
Evan Cheng
ad9c0a3d8b Use sbb x, x to materialize carry bit in a GPR. The result is all one's or all zero's. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91381 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-15 00:53:42 +00:00
Dan Gohman
22f6526081 Fix a minor inconsistency. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90165 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-30 23:33:37 +00:00
Evan Cheng
6cccc30679 MOV64rm should be marked isReMaterializable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89019 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-17 00:55:55 +00:00
Anton Korobeynikov
3a639a07ea Do not infer the target type for COPY_TO_REGCLASS from dest regclass, this won't work if it can contain several types. Require explicit result type for the node for now. This fixes PR5364. 
PS: It seems that blackfin usage of copy_to_regclass is completely bogus!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85766 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-02 00:11:39 +00:00
Dan Gohman
f705adbe5e Initial x86 support for BlockAddresses. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85557 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-30 01:28:02 +00:00
Dan Gohman
533297b58d Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a 
bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85517 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-29 18:10:34 +00:00
Chris Lattner
172862a2a7 remove strings from instructions who are never asmprinted. 
All of these "subreg32" modifier instructions are handled
explicitly by the MCInst lowering phase.  If they got to
the asmprinter, they would explode.  They should eventually
be replace with correct use of subregs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84526 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 19:51:42 +00:00
Torok Edwin
6602922878 Fix PR5247, "lock addq" pattern (and other atomics), it DOES modify EFLAGS. 
LLC was scheduling compares before the adds causing wrong branches to be taken
in programs, resulting in misoptimized code wherever atomic adds where used.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84485 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 11:00:58 +00:00
Dan Gohman
e220c4b3d9 Add support for using the FLAGS result of or, xor, and and instructions 
on x86, to avoid explicit test instructions. A few existing tests changed
due to arbitrary register allocation differences.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82263 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-18 19:59:53 +00:00
Sean Callanan
a2dc2825fc Added RCL and RCR (rotate left and right with a 
carry bit) instructions to the Intel instruction
tables.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82260 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-18 19:35:23 +00:00
Sean Callanan
9a86f10875 Added the LODS (load byte into register, usually 
as part string parsing) instructions to the Intel
instruction tables.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82089 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-16 22:59:28 +00:00
Sean Callanan
358f1ef765 Added the LAR (load segment access rights) 
instructions to the Intel instruction tables.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82084 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-16 21:55:34 +00:00
Sean Callanan
d2125a03af Added an alternate form of register-register CMP 
to the Intel instruction tables.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82081 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-16 21:11:23 +00:00
Sean Callanan
13cf8e9b82 Added the definitions for one-bit left shifts to 
the Intel instruction tables.

The patterns will stay blank because ADD reg, reg
is faster, but having the encoding available is
useful for the disassembler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81994 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-16 02:28:43 +00:00
Sean Callanan
62c28e3f91 Updated comments per Eli's suggestion. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81923 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-15 21:43:27 +00:00
Sean Callanan
37be5903a6 Added register-to-register ADD instructions to the 
Intel tables, where the source operand is
specified by the R/M field and the destination
operand by the Reg field.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81914 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-15 20:53:57 +00:00
Sean Callanan
38fee0edcf Added a new register class for segment registers 
to the Intel register table.
Added 16- and 64-bit MOVs to and from the segment
registers to the Intel instruction tables.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81895 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-15 18:47:29 +00:00
Dan Gohman
907355caf8 On x86-64, the 32-bit cmov doesn't actually clear the high 32-bit of 
its result if the condition is false.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81814 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-15 00:14:11 +00:00
Sean Callanan
6f8f462ba5 Added CMPS (string comparison) instructions for all 
operand widths to the Intel instruction tables, for
the purposes of the disassembler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81601 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-12 02:25:20 +00:00
Sean Callanan
a82e4656b0 Added SCAS instructions in their 8, 16, 32, and 
64-bit variants for the disassembler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81591 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-12 00:37:19 +00:00
Sean Callanan
d00025a6c8 Added ADC, SUB, SBB, and OR instructions that operate 
on rAX and an immediate.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81551 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-11 19:01:56 +00:00
Sean Callanan
7893ec6494 Added XOR instructions for rAX and immediates of 
various widths.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81458 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-10 19:52:26 +00:00
Sean Callanan
2f34a136b5 Added MOV instructions between rAX and memory offsets, 
including segment offsets and (for 8-bit operands)
absolute offsets.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81457 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-10 18:33:42 +00:00
Sean Callanan
1f24e01b87 Added a variety of PUSH and POP instructions, including 
ones capable of accessing R/M operands instead of just
registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81456 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-10 18:29:13 +00:00
Dan Gohman
2f67df794a Add a -disable-16bit flag and associated support for experimenting with 
disabling the use of 16-bit operations on x86. This doesn't yet work for
inline asms with 16-bit constraints, vectors with 16-bit elements,
trampoline code, and perhaps other obscurities, but it's enough to try
some experiments.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80930 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-03 17:18:51 +00:00
Sean Callanan
9947bbb297 Added opaque 32-, 48-, and 80-bit memory operand types to the X86 
instruction tables to support segmented addressing (and other objects
of obscure type).
Modified the X86 assembly printers to handle these new operand types.
Added JMP and CALL instructions that use segmented addresses.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80857 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-03 00:04:47 +00:00
Sean Callanan
a09caa56d6 Fixed the asmstrings for 8-bit, 16-bit, and 32-bit ADD %rAX, imm instructions. 
Added a 64-bit ADD %RAX, imm32 instruction.
Added all 4 forms for AND %rAX, imm and CMP %rAX, imm.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80746 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-02 00:55:49 +00:00
Sean Callanan
4a93b71fe7 Added TEST %rAX, $imm instructions to the Intel tables. These are required for the X86 disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80696 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-01 18:14:18 +00:00
Dan Gohman
af70e5c676 Don't use INSERT_SUBREG to model anyext operations on x86-64, as it 
leads to partial-register definitions. To help avoid redundant
zero-extensions, also teach the h-register matching patterns that
use movzbl to match anyext as well as zext.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80099 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-26 14:59:13 +00:00
Daniel Dunbar
0c420fc20a X86/AsmParser: Mark MOV64GSrm, MOV64FSrm, GS_MOV32rm, FS_MOV32rm as codegen only. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78733 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-11 22:24:40 +00:00
Chris Lattner
02552decf9 move some 32-bit instrs to x86instrinfo.td 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78680 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-11 16:58:39 +00:00
Daniel Dunbar
44f63f9335 llvm-mc/AsmParser: Disambiguate i64i8imm. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78598 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-10 21:06:41 +00:00
Daniel Dunbar
338825c192 llvm-mc/AsmMatcher: Change assembler parser match classes to their own record 
structure.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78581 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-10 18:41:10 +00:00
Daniel Dunbar
98164afb01 Extend comment on ParserMatchClass .td field, and add some missing 
classes for X86.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78524 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-09 06:00:04 +00:00
Anton Korobeynikov
941222eea0 Do not generate 32-bit call on win64 when imm does not fit 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78443 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-07 23:59:21 +00:00
Anton Korobeynikov
d7697d0167 We need to sext global addresses in kernel code model, not zext 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78299 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-06 11:23:24 +00:00
Dan Gohman
74f6f9a931 Enable the new no-SP register classes by default. This is to address 
PR4572. A few tests have some minor code regressions due to different
coalescing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78217 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 17:40:24 +00:00
Dan Gohman
98ca4f2a32 Major calling convention code refactoring. 
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.

This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.

This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78142 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 01:29:28 +00:00
Anton Korobeynikov
cf6b739d3d Unbreak Win64 CC. Step one: honour register save area, fix some alignment and provide a different set of call-clobberred registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77962 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-03 08:12:53 +00:00
Dan Gohman
a98634ba14 Resync lea32addr and lea64addr. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77893 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-02 16:09:17 +00:00
Evan Cheng
37b7387da9 Optimize some common usage patterns of atomic built-ins __sync_add_and_fetch() and __sync_sub_and_fetch. 
When the return value is not used (i.e. only care about the value in the memory), x86 does not have to use add to implement these. Instead, it can use add, sub, inc, dec instructions with the "lock" prefix.

This is currently implemented using a bit of instruction selection trick. The issue is the target independent pattern produces one output and a chain and we want to map it into one that just output a chain. The current trick is to select it into a merge_values with the first definition being an implicit_def. The proper solution is to add new ISD opcodes for the no-output variant. DAG combiner can then transform the node before it gets to target node selection.

Problem #2 is we are adding a whole bunch of x86 atomic instructions when in fact these instructions are identical to the non-lock versions. We need a way to add target specific information to target nodes and have this information carried over to machine instructions. Asm printer (or JIT) can use this information to add the "lock" prefix.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77582 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-30 08:33:02 +00:00
Bill Wendling
7239b51694 Add the following functions: 
- SYSCALL (normal fast system call instruction) [0f 05]
- SYSENTER (system call entry instruction) [0f 34]
- SYSEXIT (system call exit instruction) [0f 35]
- SYSEXIT64 (system call exit instruction to 64-bit user code) [REX.W 0f 35]
- SYSRET (system call return instruction) [0f 07]

Patch by Sean Callanan.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76528 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-21 01:07:24 +00:00
Chris Lattner
6ef40b11f8 use SUBREG_TO_REG instead of INSERT_SUBREG, this way the code 
generator can know the top bits are zero, not undefined.
Thanks to Dan for pointing this out.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75899 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 06:31:37 +00:00
Chris Lattner
9ac7542bab reapply r75408, which eliminates MOV64r0 in favor of using 
MOV32r0 + subregs to do the same thing.  This should work now
that PR4544 is fixed.  Thanks Evan!



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75671 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-14 20:19:57 +00:00
Bill Wendling
69600cae95 Temporarily revert r75408. It appears to break the Apple-style builds: 
x86_64-apple-darwin10-gcc -c   -g -O2  -DIN_GCC   -W -Wall -Wwrite-strings -Wstrict-prototypes -Wmissing-prototypes -pedantic -Wno-long-long -Wno-variadic-macros -Wno-overlength-strings -Wold-style-definition -Wmissing-format-attribute   -mdynamic-no-pic -DHAVE_CONFIG_H -I. -I. -I/Volumes/Sandbox/Buildbot/llvm/build.llvm-gcc-x86_64-darwin10-selfhost/build/llvmgcc42.roots/llvmgcc42~obj/src/gcc -I/Volumes/Sandbox/Buildbot/llvm/build.llvm-gcc-x86_64-darwin10-selfhost/build/llvmgcc42.roots/llvmgcc42~obj/src/gcc/. -I/Volumes/Sandbox/Buildbot/llvm/build.llvm-gcc-x86_64-darwin10-selfhost/build/llvmgcc42.roots/llvmgcc42~obj/src/gcc/../include -I./../intl -I/Volumes/Sandbox/Buildbot/llvm/build.llvm-gcc-x86_64-darwin10-selfhost/build/llvmgcc42.roots/llvmgcc42~obj/src/gcc/../libcpp/include  -I/Volumes/Sandbox/Buildbot/llvm/build.llvm-gcc-x86_64-darwin10-selfhost/build/llvmgcc42.roots/llvmgcc42~obj/src/gcc/../libdecnumber -I../libdecnumber -I/Volumes/Sandbox/Buildbot/llvm/build.llvm-gcc-x86_64-darwin10-selfhost/build/llvmCore.roots/llvmCore~dst/Developer/usr/local/include -I/Volumes/Sandbox/Buildbot/llvm/build.llvm-gcc-x86_64-darwin10-selfhost/build/llvmCore.roots/llvmCore~obj/src/include -DENABLE_LLVM -I/Volumes/Sandbox/Buildbot/llvm/build.llvm-gcc-x86_64-darwin10-selfhost/build/llvmCore.roots/llvmCore~dst/Developer/usr/local/include  -D_DEBUG  -D_GNU_SOURCE -D__STDC_LIMIT_MACROS -D__STDC_CONSTANT_MACROS -DLLVM_VERSION_INFO='"9999"' -DBUILD_LLVM_APPLE_STYLE   /Volumes/Sandbox/Buildbot/llvm/build.llvm-gcc-x86_64-darwin10-selfhost/build/llvmgcc42.roots/llvmgcc42~obj/src/gcc/tree-ssa-alias.c -o tree-ssa-alias.o
/var/tmp//ccJQ2JBT.s:4134:Incorrect register `%rcx' used with `l' suffix
make[2]: *** [tree-ssa-live.o] Error 1
make[2]: *** Waiting for unfinished jobs....



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75412 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-12 02:49:22 +00:00