Commit Graph

98 Commits

Author SHA1 Message Date
Jim Grosbach
586c0042da MC: Clean up MCExpr naming. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238634 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-30 01:25:56 +00:00
Michael Kuperstein
d714fcf5c8 Use std::bitset for SubtargetFeatures.
Previously, subtarget features were a bitfield with the underlying type being uint64_t. 
Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset.
No functional change.

The first several times this was committed (e.g. r229831, r233055), it caused several buildbot failures.
Apparently the reason for most failures was both clang and gcc's inability to deal with large numbers (> 10K) of bitset constructor calls in tablegen-generated initializers of instruction info tables. 
This should now be fixed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238192 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-26 10:47:10 +00:00
Pete Cooper
39aa893201 Remove 3 includes from MCInstrDesc.h and explicitly include them where needed
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237481 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-15 21:58:42 +00:00
Jim Grosbach
251a66ec37 MC: Update MCCodeEmitter naming. NFC.
s/EncodeInstruction/encodeInstruction/

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237469 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-15 19:13:16 +00:00
Jim Grosbach
8b22e9c00a MC: Update MCFixup naming. NFC.
s/MCFixup::Create/MCFixup::create/

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237468 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-15 19:13:05 +00:00
Michael Kuperstein
66112dd7f8 Reverting r237234, "Use std::bitset for SubtargetFeatures"
The buildbots are still not satisfied.
MIPS and ARM are failing (even though at least MIPS was expected to pass).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237245 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-13 10:28:46 +00:00
Michael Kuperstein
1336daad86 Use std::bitset for SubtargetFeatures
Previously, subtarget features were a bitfield with the underlying type being uint64_t. 
Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset.
No functional change.

The first two times this was committed (r229831, r233055), it caused several buildbot failures. 
At least some of the ARM and MIPS ones were due to gcc/binutils issues, and should now be fixed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237234 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-13 08:27:08 +00:00
Zoran Jovanovic
d311051513 [mips][microMIPSr6] Implement mips32 to microMIPSr6 mapping support
Differential Revision: http://reviews.llvm.org/D8661


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235505 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-22 13:27:34 +00:00
Jozef Kolek
7ab9941632 [mips][microMIPSr6] Implement initial mapping support
Differential Revision: http://reviews.llvm.org/D8387


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235298 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-20 12:42:08 +00:00
Jozef Kolek
ec47ed84d2 [mips][microMIPSr6] Implement initial subtarget support
Differential Revision: http://reviews.llvm.org/D8386


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235296 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-20 12:23:06 +00:00
Michael Kuperstein
765aab84d6 Revert "Use std::bitset for SubtargetFeatures"
This reverts commit r233055.

It still causes buildbot failures (gcc running out of memory on several platforms, and a self-host failure on arm), although less than the previous time.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233068 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-24 12:56:59 +00:00
Michael Kuperstein
d3ab717935 Use std::bitset for SubtargetFeatures
Previously, subtarget features were a bitfield with the underlying type being uint64_t. 
Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset.
No functional change.

The first time this was committed (r229831), it caused several buildbot failures. 
At least some of the ARM ones were due to gcc/binutils issues, and should now be fixed.

Differential Revision: http://reviews.llvm.org/D8542

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233055 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-24 09:17:25 +00:00
Daniel Sanders
547ba56bd0 Recommit r232027 with PR22883 fixed: Add infrastructure for support of multiple memory constraints.
The operand flag word for ISD::INLINEASM nodes now contains a 15-bit
memory constraint ID when the operand kind is Kind_Mem. This constraint
ID is a numeric equivalent to the constraint code string and is converted
with a target specific hook in TargetLowering.

This patch maps all memory constraints to InlineAsm::Constraint_m so there
is no functional change at this point. It just proves that using these
previously unused bits in the encoding of the flag word doesn't break
anything.

The next patch will make each target preserve the current mapping of
everything to Constraint_m for itself while changing the target independent
implementation of the hook to return Constraint_Unknown appropriately. Each
target will then be adapted in separate patches to use appropriate
Constraint_* values.

PR22883 was caused the matching operands copying the whole of the operand flags
for the matched operand. This included the constraint id which needed to be
replaced with the operand number. This has been fixed with a conversion
function. Following on from this, matching operands also used the operand
number as the constraint id. This has been fixed by looking up the matched
operand and taking it from there. 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232165 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-13 12:45:09 +00:00
Eric Christopher
57849e3bb4 Remove the use of the subtarget in MCCodeEmitter creation and
update all ports accordingly. Required a couple of small rewrites
in handling subtarget features during creation in PPC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231861 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-10 22:03:14 +00:00
Michael Kuperstein
2b5910a767 Reverting r229831 due to multiple ARM/PPC/MIPS build-bot failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229841 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-19 11:38:11 +00:00
Michael Kuperstein
23dd089d8f Use std::bitset for SubtargetFeatures
Previously, subtarget features were a bitfield with the underlying type being uint64_t. 
Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset.

No functional change.

Differential Revision: http://reviews.llvm.org/D7065

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229831 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-19 09:01:04 +00:00
Zoran Jovanovic
3c53772000 [mips][microMIPS] Implement movep instruction
Differential Revision: http://reviews.llvm.org/D7465


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228703 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-10 16:36:20 +00:00
Jozef Kolek
a8c8e06c02 [mips][microMIPS] Implement LWGP instruction
Differential Revision: http://reviews.llvm.org/D6650


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227325 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-28 17:27:26 +00:00
Jozef Kolek
db8552c834 [mips][microMIPS] MicroMIPS 16-bit unconditional branch instruction B
Implement microMIPS 16-bit unconditional branch instruction B.

Implemented 16-bit microMIPS unconditional instruction has real name B16, and
B is an alias which expands to either B16 or BEQ according to the rules:
b 256 --> b16 256 # R_MICROMIPS_PC10_S1
b 12256 --> beq $zero, $zero, 12256 # R_MICROMIPS_PC16_S1
b label --> beq $zero, $zero, label # R_MICROMIPS_PC16_S1

Differential Revision: http://reviews.llvm.org/D3514


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226657 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-21 12:39:30 +00:00
Jozef Kolek
16dbcd741f [mips][microMIPS] Implement ADDIUPC instruction
Differential Revision: http://reviews.llvm.org/D6582


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226656 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-21 12:10:11 +00:00
Jozef Kolek
8832c6b91e Reverted revision 226577.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226595 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-20 19:29:28 +00:00
Jozef Kolek
617b574ffb [mips][microMIPS] MicroMIPS 16-bit unconditional branch instruction B
Implement microMIPS 16-bit unconditional branch instruction B.

Implemented 16-bit microMIPS unconditional instruction has real name B16, and
B is an alias which expands to either B16 or BEQ according to the rules:
b 256 --> b16 256 # R_MICROMIPS_PC10_S1
b 12256 --> beq $zero, $zero, 12256 # R_MICROMIPS_PC16_S1
b label --> beq $zero, $zero, label # R_MICROMIPS_PC16_S1

Differential Revision: http://reviews.llvm.org/D3514


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226577 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-20 16:45:27 +00:00
Chandler Carruth
1b279144ec [cleanup] Re-sort all the #include lines in LLVM using
utils/sort_includes.py.

I clearly haven't done this in a while, so more changed than usual. This
even uncovered a missing include from the InstrProf library that I've
added. No functionality changed here, just mechanical cleanup of the
include order.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225974 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-14 11:23:27 +00:00
Jozef Kolek
ad017096fc [mips][microMIPS] Implement BEQZ16 and BNEZ16 instructions
Differential Revision: http://reviews.llvm.org/D5271


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225627 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-12 12:03:34 +00:00
Jozef Kolek
e5fa612e9e [mips][microMIPS] Implement LWSP and SWSP instructions
Differential Revision: http://reviews.llvm.org/D6416


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224771 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-23 16:16:33 +00:00
Zoran Jovanovic
78f6aad800 [mips][microMIPS] Implement SWP and LWP instructions
Differential Revision: http://reviews.llvm.org/D5667


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224338 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-16 14:59:10 +00:00
Jozef Kolek
b087448a5f [mips][microMIPS] Implement NOP aliases
This patch implements microMIPS 16-bit (MOVE16 $0, $0) and
32-bit (SLL $0, $0, 0) NOP aliases.

http://reviews.llvm.org/D6440


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222953 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-29 13:29:24 +00:00
Zoran Jovanovic
7dc6143a82 [mips][microMIPS] Implement SWM16 and LWM16 instructions
Differential Revision: http://reviews.llvm.org/D5579


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222901 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-27 18:28:59 +00:00
Jozef Kolek
b955bed064 [mips][microMIPS] Implement LBU16, LHU16, LW16, SB16, SH16 and SW16 instructions
Differential Revision: http://reviews.llvm.org/D5122


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222653 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-24 14:39:13 +00:00
Zoran Jovanovic
d67cd80220 [mips][micromips] Implement SWM32 and LWM32 instructions
Differential Revision: http://reviews.llvm.org/D5519


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222367 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-19 16:44:02 +00:00
Zoran Jovanovic
8dad1e1e8e [mips][microMIPS] Implement ANDI16 instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221367 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-05 17:31:00 +00:00
Zoran Jovanovic
e9b9ca452f Reverted revisions 221351, 221352 and 221353.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221354 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-05 16:19:59 +00:00
Zoran Jovanovic
7c63a6331f [mips][microMIPS] Implement ANDI16 instruction
Differential Revision: http://reviews.llvm.org/D5163


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221351 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-05 15:39:41 +00:00
Zoran Jovanovic
71832e7ed9 [mips][microMIPS] Implement ADDIUR1SP instruction
Differential Revision: http://reviews.llvm.org/D5153


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220477 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-23 11:13:59 +00:00
Zoran Jovanovic
fd515137bc ps][microMIPS] Implement ADDIUR2 instruction
Differential Revision: http://reviews.llvm.org/D5151


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220476 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-23 11:06:34 +00:00
Zoran Jovanovic
558236adf0 [mips][microMIPS] Implement CodeGen support for SLL16 and SRL16 instructions
Differential Revision: http://reviews.llvm.org/D5774


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220474 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-23 10:42:01 +00:00
Zoran Jovanovic
0bf4807a90 [mips][microMIPS] Implement ADDIUSP instruction
Differential Revision: http://reviews.llvm.org/D5084


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219500 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-10 14:37:30 +00:00
Zoran Jovanovic
614d8681e0 [mips][microMIPS] Implement JRADDIUSP instruction
Differential Revision: http://reviews.llvm.org/D5046


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217681 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-12 14:29:54 +00:00
Zoran Jovanovic
636ae2b660 [mips][mips64r6] Relocation R_MIPS_PC18_S3
Differential Revision: http://reviews.llvm.org/D3890


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210908 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-13 14:26:47 +00:00
Zoran Jovanovic
10ce787fa5 [mips][mips64r6] Add R_MIPS_PC19_S2
Differential Revision: http://reviews.llvm.org/D3866


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210773 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-12 12:40:00 +00:00
Zoran Jovanovic
0c7ac480e2 [mips][mips64r6] Add LDPC instruction
Differential Revision: http://reviews.llvm.org/D3822


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210460 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-09 09:49:51 +00:00
Zoran Jovanovic
61e341e0bf [mips][mips64r6] Add Relocations R_MIPS_PCHI16, R_MIPS_PCLO16
Differential Revision: http://reviews.llvm.org/D3860


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209659 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-27 14:58:51 +00:00
Zoran Jovanovic
f7744906f0 [mips][mips64r6] Add relocations R_MIPS_PC21_S2, R_MIPS_PC26_S2
Differential Revision: http://reviews.llvm.org/D3824


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209655 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-27 12:55:40 +00:00
Zoran Jovanovic
b95580a711 [mips][mips64r6] Add Compact indexed jumps.
Differential Revision: http://reviews.llvm.org/D3707


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208981 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-16 13:19:46 +00:00
Zoran Jovanovic
b8c3bcbbfa [mips][mips64r6] Add compact branch instructions
Differential Revision: http://reviews.llvm.org/D3691


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208974 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-16 11:03:45 +00:00
Daniel Sanders
06961bf147 [mips][mips64r6] Add addiupc, aluipc, and auipc
Summary:
No support for symbols in place of the immediate yet since it requires new
relocations.

Depends on D3671

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3689

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208858 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15 10:45:58 +00:00
Chandler Carruth
42e8630239 [Modules] Fix potential ODR violations by sinking the DEBUG_TYPE
definition below all of the header #include lines, lib/Target/...
edition.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206842 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-22 02:41:26 +00:00
Sasa Stankovic
10914379f6 [mips] Extend MipsMCExpr class to handle %higher(sym1 - sym2 + const) and
%highest(sym1 - sym2 + const) relocations. Remove "ABS_" from VK_Mips_HI
and VK_Mips_LO enums in MipsMCExpr, to be consistent with VK_Mips_HIGHER
and VK_Mips_HIGHEST.

This change also deletes test file test/MC/Mips/higher_highest.ll and moves
its CHECK's to the new test file test/MC/Mips/higher-highest-addressing.s.
The deleted file tests that R_MIPS_HIGHER and R_MIPS_HIGHEST relocations are
emitted in the .o file. Since it uses -force-mips-long-branch option, it was
created when MipsLongBranch's implementation was emitting R_MIPS_HIGHER and
R_MIPS_HIGHEST relocations in the .o file. It was disabled when MipsLongBranch
started to directly calculate offsets.

Differential Revision: http://llvm-reviews.chandlerc.com/D3230


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205522 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-03 10:37:45 +00:00
Matheus Almeida
affc53dcde [mips] Splitting up class definition from implementation.
Also removed some unnecessary #includes.

No functional changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204320 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-20 09:29:54 +00:00
Petar Jovanovic
7f15e90281 [mips] Implement %hi(sym1 - sym2) and %lo(sym1 - sym2) expressions
Patch implements %hi(sym1 - sym2) and %lo(sym1 - sym2) expressions for MIPS
by creating target expression class MipsMCExpr.

Patch by Sasa Stankovic.

Differential Revision: http://llvm-reviews.chandlerc.com/D2592


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200783 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-04 18:41:57 +00:00