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55 Commits

Author SHA1 Message Date
Aaron Ballman
13e20a9dac Silencing a 32-bit implicit conversion warning in MSVC; NFC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223237 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-03 14:39:58 +00:00
Tom Stellard
db7067607f R600/SI: Emit amd_kernel_code_t header for AMDGPU environment 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223160 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-02 22:00:07 +00:00
Tom Stellard
d90fc9d0fc R600/SI: Move more information into SIProgramInfo struct 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223154 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-02 21:28:53 +00:00
Tom Stellard
30892329d4 R600/SI: Refactor AMDGPUAsmPrinter::EmitProgramInfoSI() 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223144 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-02 19:45:05 +00:00
Tom Stellard
77859c9e9c R600: Align functions to 256 bytes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219002 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-03 19:02:02 +00:00
Tom Stellard
56077f5796 R600: Call EmitFunctionHeader() in the AsmPrinter to populate the ELF symbol table 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218776 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-01 17:15:17 +00:00
Tom Stellard
860cabe1e6 R600/SI: Implement VGPR register spilling for compute at -O0 v3 
VGPRs are spilled to LDS.  This still needs more testing, but
we need to at least enable it at -O0, because the fast register
allocator spills all registers that are live at the end of blocks
and without this some future commits will break the
flat-address-space.ll test.

v2: Only calculate thread id once

v3: Move insertion of spill instructions to
    SIRegisterInfo::eliminateFrameIndex()

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218348 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-09-24 01:33:17 +00:00
Tom Stellard
ea28172c61 R600/SI: Fix config value for number of gprs 
In r217636, the value stored in KernelInfo.Num[VS]GPRSs was changed from
the highest GPR index used to the number of gprs in order to be
consistent with the name of the variable.

The code writing the config values still assumed that the value in this
variable was the highest GPR index used, which caused the compiler to
over report the number of GPRs being used.

https://bugs.freedesktop.org/show_bug.cgi?id=84089

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218150 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-09-19 20:42:37 +00:00
Matt Arsenault
d189a0407d R600/SI: Add preliminary support for flat address space 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217777 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-09-15 15:41:53 +00:00
Matt Arsenault
86ffcddf42 R600/SI: Fix off by 1 error in used register count 
The register numbers start at 0, so if only 1 register
was used, this was reported as 0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217636 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-09-11 22:51:37 +00:00
Eric Christopher
9f85dccfc6 Remove the TargetMachine forwards for TargetSubtargetInfo based 
information and update all callers. No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214781 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-08-04 21:25:23 +00:00
Tom Stellard
3280804237 R600/SI: Use scratch memory for large private arrays 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213551 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-07-21 15:45:01 +00:00
Tom Stellard
b664d47cb0 R600/SI: Store constant initializer data in constant memory 
This implements a solution for constant initializers suggested
by Vadim Girlin, where we store the data after the shader code
and then use the S_GETPC instruction to compute its address.

This saves use the trouble of creating a new buffer for constant data
and then having to pass the pointer to the kernel via user SGPRs or the
input buffer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213530 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-07-21 14:01:14 +00:00
Matt Arsenault
b7df516d1f R600: Add denormal handling subtarget features. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213018 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-07-14 23:40:49 +00:00
Matt Arsenault
5b70c8ac7e R600/SI: Default to no single precision denormals. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213017 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-07-14 23:40:43 +00:00
Matt Arsenault
74c9fe26e6 R600: Use range for and fix missing consts. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212897 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-07-13 03:06:43 +00:00
Matt Arsenault
bb098a4d87 R600: Make ShaderType private 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212896 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-07-13 03:06:39 +00:00
Matt Arsenault
3cd8cf6bbd R600/SI: Add FP mode bits to binary. 
The default rounding mode to initialize the mode register needs
to be reported to the runtime. Fill in other bits a kernel
may be interested in setting for future use.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211791 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-26 17:22:30 +00:00
Tom Stellard
6b0a08b15b R600: Move AMDGPUInstrInfo from AMDGPUTargetMachine into AMDGPUSubtarget 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210869 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-13 01:32:00 +00:00
Matt Arsenault
d66d570796 R600/SI: Print code size along with used registers 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206336 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-15 22:40:47 +00:00
Tom Stellard
eb7876083d R600/SI: Use correct dest register class for V_READFIRSTLANE_B32 
This instructions writes to an 32-bit SGPR.  This change required adding
the 32-bit VCC_LO and VCC_HI registers, because the full VCC register
is 64 bits.

This fixes verifier errors on several of the indirect addressing piglit
tests.

Tested-by: Michel Dänzer <michel.daenzer@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204055 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-17 17:03:51 +00:00
Rafael Espindola
b9e06b97ce Remove MCPureStreamer. 
We moved MCJIT to use native object formats a long time ago and R600
now uses ELF, so it was dead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202408 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-27 16:17:34 +00:00
Rafael Espindola
9d96045528 Remove the last hasRawTextSupport call from R600. 
There is nothing wrong with printing the disassembly section when printing
text. An hypothetical assembler would then produce a .o just like our
direct object emission produces.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200583 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-31 22:14:06 +00:00
Rafael Espindola
b8f1606076 Replace another use with hasRawTextSupport+EmitRawText with emitRawComment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200582 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-31 22:08:19 +00:00
Rafael Espindola
f7af9eac1b Use emitRawComment to avoid a call to hasRawTextSupport. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200581 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-31 21:54:49 +00:00
Rafael Espindola
888177e91b Add back spaces I missed in the conversion to emitRawComments. 
Sorry about that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200171 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-27 00:19:41 +00:00
Rafael Espindola
e881f38db6 Use emitRawComment instead of EmitRawText. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200170 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-27 00:16:00 +00:00
Tom Stellard
0ed0ced91c R600: Add stack size to .AMDGPUcsdata section 
reviewed-by: Vincent Lejeune <vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199837 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-22 21:55:35 +00:00
Matt Arsenault
b9271b0ec5 Move declaration of variables down to first use. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198794 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-08 21:47:14 +00:00
Matt Arsenault
17427fa9bb Use llvm_unreachable instead of assert(0) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196971 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-10 21:37:42 +00:00
Matt Arsenault
87234703e8 R600/SI: Add comments for number of used registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196467 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-05 05:15:35 +00:00
Matt Arsenault
29a651af8a Indentation fixes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194688 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-14 10:08:50 +00:00
Tom Stellard
54328c772c R600/SI: Add compute support for CI v2 
v2:
  - Fix LDS size calculation

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193621 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-29 16:37:28 +00:00
Tom Stellard
f9e5c39811 R600/SI: Use S_LOAD_DWORD instructions for v8i32 and v16i32 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193212 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-23 00:44:12 +00:00
Matt Arsenault
8305cae004 R600/SI: Don't assert on SCC usage 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193198 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-22 21:11:31 +00:00
Tom Stellard
f931867317 R600: Store disassembly in a special ELF section when feature +DumpCode is enabled. 
Patch by: Jay Cornwall

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192523 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-12 05:02:51 +00:00
Michel Danzer
a3e39dc705 R600/SI: Initial local memory support 
Enough for the radeonsi driver to use it for calculating derivatives.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186012 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-10 16:37:07 +00:00
Tom Stellard
e3d4cbc7d2 R600: Add local memory support via LDS 
Reviewed-by: Vincent Lejeune<vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185162 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-28 15:47:08 +00:00
Tom Stellard
3ff0abfaab R600: Rework subtarget info and remove AMDILDevice classes 
This should simplify the subtarget definitions and make it easier to
add new ones.

Reviewed-by: Vincent Lejeune <vljn@ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183566 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 20:37:48 +00:00
Benjamin Kramer
5c35290fa3 Move passes from namespace llvm into anonymous namespaces. Sort includes while there. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182594 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-23 17:10:37 +00:00
Tom Stellard
f07b5373d7 R600: Emit config values in register / value pairs 
Reviewed-by: Vincent Lejeune <vljn@ovi.com>
Tested-By: Aaron Watry <awatry@gmail.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181228 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-06 17:50:51 +00:00
Vincent Lejeune
86cdb70417 R600: config section now reports use of killgt 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180751 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-30 00:13:13 +00:00
Tom Stellard
87cba4a4c1 R600: Use SHT_PROGBITS for the .AMDGPU.config section 
The libelf implementation that is distributed here:
http://www.mr511.de/software/english.html
will not parse sections that are marked SHT_NULL.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180230 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-24 23:56:14 +00:00
Vincent Lejeune
2a74639bc7 R600: Use .AMDGPU.config section to emit stacksize 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180124 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-23 17:34:12 +00:00
Vincent Lejeune
141ca7fc64 R600: Emit used GPRs count 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179684 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-17 15:17:25 +00:00
Tom Stellard
9a256300f8 R600/SI: Emit config values in register value pairs. 
Instead of emitting config values in a predefined order, the code
emitter will now emit a 32-bit register index followed by the 32-bit
config value.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179546 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-15 17:51:35 +00:00
Tom Stellard
bf1efe6421 R600/SI: Emit configuration value in the .AMDGPU.config ELF section 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179545 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-15 17:51:30 +00:00
Christian Konig
4d0e8a8a3e R600/SI: dynamical figure out the reg class of MIMG 
Depending on the number of bits set in the writemask.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179166 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-10 08:39:16 +00:00
Christian Konig
cc22640c4c R600/SI: rework input interpolation v2 
v2: update CMakeLists.txt as well

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176626 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-07 09:04:14 +00:00
Christian Konig
e25e490793 R600/SI: cleanup literal handling v3 
Seems to be allot simpler, and also paves the
way for further improvements.

v2: rebased on master, use 0 in BUFFER_LOAD_FORMAT_XYZW,
    use VGPR0 in dummy EXP, avoid compiler warning, break
    after encoding the first literal.
v3: correctly use V_ADD_F32_e64

This is a candidate for the stable branch.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175354 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-16 11:28:22 +00:00