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Author SHA1 Message Date
Evan Cheng c546c75459 Remove disabled assertion. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111531 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-19 17:33:48 +00:00
Evan Cheng 4dc301a7c5 Teach machine-sink to break critical edges when appropriate. Work in progress. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111530 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-19 17:33:11 +00:00
Evan Cheng c3439ad63f If any def of a machine-sink candidate has local uses, it's obviously not safe to sink it to a successor block. This bug has been hidden because a later check for critical-edge disable these illegal optimizations. This patch should significantly reduce the amount of time spent on checking dominator information for obviously unsafe sinking. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111450 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-18 23:09:25 +00:00
Evan Cheng b9072fdaad Add nounwind. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111312 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-17 22:35:20 +00:00
Evan Cheng 148341cc9b PHI elimination shouldn't require machineloopinfo since it's used at -O0. Move the requirement to LiveIntervalAnalysis instead. Note this does not change the number of times machineloopinfo is computed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111285 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-17 21:00:37 +00:00
Evan Cheng 6542416560 Machine CSE preserves CFG. Pass manager was freeing machineloopinfo after machine cse before. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111281 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-17 20:57:42 +00:00
Evan Cheng e008384508 Move the decision logic whether it's a good idea to split a critical edge to clients. Also fixed an erroneous check. An edge is only a back edge when the from and to blocks are in the same loop. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111256 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-17 17:43:50 +00:00
Evan Cheng 087fbeb7d1 Fix debug message. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111250 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-17 17:15:14 +00:00
Evan Cheng e1bcb440dc Add an option to disable codegen prepare critical edge splitting. In theory, PHI elimination is already doing all (most?) of the splitting needed. But machine-licm and machine-sink seem to miss some important optimizations when splitting is disabled. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111224 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-17 01:34:49 +00:00
Evan Cheng 97b9b97853 PHI elimination should not break back edge. It can cause some significant code placement issues. rdar://8263994 
good:
LBB0_2:
  mov     r2, r0
  . . .
  mov     r1, r2
  bne     LBB0_2

bad:
LBB0_2:
  mov     r2, r0
  . . .
@ BB#3:
  mov     r1, r2
  b       LBB0_2


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111221 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-17 01:20:36 +00:00
Evan Cheng 719510a178 Make sure ARM constant island pass does not break up an IT block. If the split point is in the middle of an IT block, it should move it up to just above the IT instruction. rdar://8302637 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110947 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-12 20:30:05 +00:00
Evan Cheng e1f0859789 Fix test and re-enable it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110829 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 17:25:51 +00:00
Evan Cheng 7b4d31176e Report error if codegen tries to instantiate a ARM target when the cpu does support it. e.g. cortex-m* processors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110798 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 07:17:46 +00:00
Evan Cheng 8d62e713ea ArchV7M implies HW division instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110797 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 07:00:16 +00:00
Evan Cheng cb5ce6e62b ArchV6T2, V7A, and V7M implies Thumb2; Archv7A implies NEON. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110796 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 06:57:53 +00:00
Evan Cheng d6b4632256 Add ARM Archv6M and let it implies FeatureDB (having dmb, etc.) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110795 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 06:51:54 +00:00
Evan Cheng ee34987fd5 Really control isel of barrier instructions with cpu feature. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110787 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 06:36:31 +00:00
Evan Cheng c7569ed4e4 Add Cortex-M0 support. It's a ARMv6m device (no ARM mode) with some 32-bit 
instructions: dmb, dsb, isb, msr, and mrs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110786 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 06:30:38 +00:00
Evan Cheng 11db068721 - Add subtarget feature -mattr=+db which determine whether an ARM cpu has the 
memory and synchronization barrier dmb and dsb instructions.
- Change instruction names to something more sensible (matching name of actual
  instructions).
- Added tests for memory barrier codegen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110785 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 06:22:01 +00:00
Evan Cheng 3611d9e25d CBZ and CBNZ are implemented. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110745 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-10 23:27:11 +00:00
Evan Cheng 5818032521 Delete some unused instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110710 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-10 19:36:22 +00:00
Evan Cheng ac096808a3 Re-apply r110655 with fixes. Epilogue must restore sp from fp if the function stack frame has a var-sized object. 
Also added a test case to check for the added benefit of this patch: it's optimizing away the unnecessary restore of sp from fp for some non-leaf functions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110707 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-10 19:30:19 +00:00
Evan Cheng c9aed19747 Fix ARM hasFP() semantics. It should return true whenever FP register is 
reserved, not available for general allocation. This eliminates all the
extra checks for Darwin.

This change also fixes the use of FP to access frame indices in leaf
functions and cleaned up some confusing code in epilogue emission.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110655 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-10 06:26:49 +00:00
Evan Cheng c120af4567 Add missing null check reported by Amaury Pouly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110649 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-10 02:39:45 +00:00
Evan Cheng b000d683c8 ARMBaseRegisterInfo::hasFP() has been broken for a while now. :-( 
This will always be false before PEI:
(DisableFramePointerElim(MF) && MFI->adjustsStack())
Which means it's going to make r11 available as a general purpose register even
if -disable-fp-elim is specified. It's working on Darwin only because r7 is
always reserved. But it's obviously broken for other targets.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110614 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-09 22:32:45 +00:00
Evan Cheng 9de1ac267e Explicitly initialize SlowFPBrcc and Pref32BitThumb to false. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110587 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-09 19:19:36 +00:00
Evan Cheng e44be63816 Change -prefer-32bit-thumb to attribute -mattr=+32bit instead to disable more 32-bit to 16-bit optimizations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110584 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-09 18:35:19 +00:00
Evan Cheng e8846feaa1 Add an option to disable 32 -> 16-bit Thumb2 size reduction pass for experimentation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110579 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-09 17:16:10 +00:00
Evan Cheng a2c519bd0b Add -disable-shifter-op to disable isel of shifter ops. On Cortex-a9 the shifts cost extra instructions so it might be better to emit them separately to take advantage of dual-issues. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109934 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-30 23:33:54 +00:00
Evan Cheng dee81010eb On x86, f32 / f64 nodes share the same registers as 128-bit vector values. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109450 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-26 21:50:05 +00:00
Evan Cheng e0e925efb3 The "excess register pressure" returned by HighRegPressure() is not accurate enough to factor into scheduling priority. Eliminate it and add early exits to speed up scheduling. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109449 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-26 21:49:07 +00:00
Evan Cheng 0944795b8c ARM fastisel isn't ready. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109421 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-26 18:32:55 +00:00
Evan Cheng e28ed16d25 Add comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109383 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-25 18:59:43 +00:00
Evan Cheng 70017e44cd Add an ILP scheduler. This is a register pressure aware scheduler that's 
appropriate for targets without detailed instruction iterineries.
The scheduler schedules for increased instruction level parallelism in
low register pressure situation; it schedules to reduce register pressure
when the register pressure becomes high.

On x86_64, this is a win for all tests in CFP2000. It also sped up 256.bzip2
by 16%.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109300 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-24 00:39:05 +00:00
Evan Cheng 3144687df7 - Allow target to specify when is register pressure "too high". In most cases, 
it's too late to start backing off aggressive latency scheduling when most
  of the registers are in use so the threshold should be a bit tighter.
- Correctly handle live out's and extract_subreg etc.
- Enable register pressure aware scheduling by default for hybrid scheduler.
  For ARM, this is almost always a win on # of instructions. It's runtime
  neutral for most of the tests. But for some kernels with high register
  pressure it can be a huge win. e.g. 464.h264ref reduced number of spills by
  54 and sped up by 20%.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109279 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-23 22:39:59 +00:00
Evan Cheng 89ba74d117 Re-apply r109079 with fix. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109083 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-22 06:24:48 +00:00
Evan Cheng a4081238aa Initialize RegLimit only when register pressure is being tracked. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109079 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-22 05:18:41 +00:00
Evan Cheng b1c857bb7b Fix constant island pass's handling of tBR_JTr. The offset of the instruction does not have to be 4-byte aligned. Rather, it's the offset + 2 that must be aligned since the instruction expands into: 
mov     pc, r1
        .align  2
LJTI0_0_0:
        .long    LBB0_14

This fixes rdar://8213383. No test case since it's not possible to come up with a suitable small one.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109076 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-22 02:09:47 +00:00
Evan Cheng 4a863e2c75 More register pressure aware scheduling work. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109064 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-21 23:53:58 +00:00
Evan Cheng 4f6b4674be Teach bottom up pre-ra scheduler to track register pressure. Work in progress. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108991 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-21 06:09:07 +00:00
Evan Cheng d70f57b254 ARM has to provide its own TargetLowering::findRepresentativeClass because its scalar floating point registers alias its vector registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108761 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-19 22:15:08 +00:00
Evan Cheng 46dcb57e18 Teach computeRegisterProperties() to compute "representative" register class for legal value types. A "representative" register class is the largest legal super-reg register class for a value type. e.g. On i386, GR32 is the rep register class for i8 / i16 / i32; on x86_64 it would be GR64. 
This property will be used by the register pressure tracking instruction scheduler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108735 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-19 18:47:01 +00:00
Evan Cheng 60108e96bb Split -enable-finite-only-fp-math to two options: 
-enable-no-nans-fp-math and -enable-no-infs-fp-math. All of the current codegen fp math optimizations only care whether the fp arithmetics arguments and results can never be NaN.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108465 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-15 22:07:12 +00:00
Evan Cheng dedd974e7e Fix for PR7193 was overly conservative. The only case where sibcall callee 
address cannot be allocated a register is in 32-bit mode where the first
three arguments are marked inreg. In that case EAX, EDX, and ECX will be
used for argument passing.

This fixes PR7610.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108327 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-14 06:44:01 +00:00
Evan Cheng 44a44ad3bc Re-enable the test with fix. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108319 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-14 05:49:23 +00:00
Evan Cheng db89809037 Teach ProcessImplicitDefs to transform more COPY instructions into IMPLICIT_DEF (and subsequently eliminate them). This allows machine LICM to hoist IMPLICIT_DEF's. PR7620. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108304 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-14 01:22:19 +00:00
Evan Cheng db20d257bc Update comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108272 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-13 21:03:14 +00:00
Evan Cheng 218977b53e Extend the r107852 optimization which turns some fp compare to code sequence using only i32 operations. It now optimize some f64 compares when fp compare is exceptionally slow (e.g. cortex-a8). It also catches comparison against 0.0. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108258 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-13 19:27:42 +00:00
Evan Cheng 7a41599962 Add an ARM "feature". Cortex-a8 fp comparison is very slow (> 20 cycles). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108256 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-13 19:21:50 +00:00
Evan Cheng ea4cdb7ead -enable-unsafe-fp-math should not imply -enable-finite-only-fp-math. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108254 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-13 18:46:14 +00:00
Evan Cheng 5d115a0ff9 Check for FiniteOnlyFPMath as well. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107904 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-08 20:12:24 +00:00
Evan Cheng 4ff7ab612c r107852 is only safe with -enable-unsafe-fp-math to account for +0.0 == -0.0. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107856 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-08 06:01:49 +00:00
Evan Cheng 515fe3a588 Optimize some vfp comparisons to integer ones. This patch implements the simplest case when the following conditions are met: 
1. The arguments are f32.
2. The arguments are loads and they have no uses other than the comparison.
3. The comparison code is EQ or NE.

e.g.
        vldr.32 s0, [r1]
        vldr.32 s1, [r0]
        vcmpe.f32       s1, s0
        vmrs    apsr_nzcv, fpscr
	beq     LBB0_2
=>
        ldr     r1, [r1]
        ldr     r0, [r0]
        cmp     r0, r1
        beq     LBB0_2

More complicated cases will be implemented in subsequent patches.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107852 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-08 02:08:50 +00:00
Evan Cheng bcc8017c73 Move getExtLoad() and (some) getLoad() DebugLoc argument after EVT argument for consistency sake. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107820 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-07 22:15:37 +00:00
Evan Cheng f2f4903687 Infer alignments of fixed frame objects when they are constructed. This ensures remat'ed loads from fixed slots have the right alignments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107591 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-04 18:52:05 +00:00
Evan Cheng ed2ae136d2 Remove isSS argument from CreateFixedObject. Fixed objects cannot be spill slots so it's always false. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107550 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-03 00:40:23 +00:00
Evan Cheng dca653951c Remove early IT block formation. It's not used. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107513 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-02 21:07:09 +00:00
Evan Cheng 98ec91ea80 - Two-address pass should not assume unfolding is always successful. 
- X86 unfolding should check if the instructions being unfolded has memoperands.
  If there is no memoperands, then it must assume conservative alignment. If this
  would introduce an expensive sse unaligned load / store, then unfoldMemoryOperand
  etc. should not unfold the instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107509 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-02 20:36:18 +00:00
Evan Cheng c36b5b9730 PR7503: uxtb16 is not available for ARMv7-M. Patch by Brian G. Lucas. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107122 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 05:38:36 +00:00
Evan Cheng c170f66742 Change if-cvt options to something that actually as useable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107121 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 05:37:59 +00:00
Evan Cheng f6799394d5 It's now possible to run code placement pass for ARM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106935 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-26 01:52:05 +00:00
Evan Cheng 13151432ed Change if-conversion block size limit checks to add some flexibility. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106901 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 22:42:03 +00:00
Evan Cheng 8acf67672b Oops. IT block formation pass needs to be run at any optimization level. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106775 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-24 19:10:14 +00:00
Evan Cheng 4d54e5b2dd Tail merging pass shall not break up IT blocks. rdar://8115404 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106517 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-22 01:18:16 +00:00
Evan Cheng d95ea2da28 Fix PR7421: bug in kill transferring logic. It was ignoring loads / stores which have already been processed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106481 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 21:21:14 +00:00
Evan Cheng 859df5e9f9 Fix a crash caused by dereference of MBB.end(). rdar://8110842 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106399 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-20 00:54:38 +00:00
Evan Cheng 02ba9e19c7 Ignore dbg_value's. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106373 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-19 02:36:21 +00:00
Evan Cheng 0110ac66eb Disable sibcall optimization for Thumb1 for now since Thumb1RegisterInfo::emitEpilogue is not expecting them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106368 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-19 01:01:32 +00:00
Evan Cheng 6523d2ff7f Indentation and remove dead code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106362 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-19 00:11:54 +00:00
Evan Cheng 96c3da6436 Move ARM if-conversion before post-ra scheduling. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106355 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 23:32:07 +00:00
Evan Cheng 3ee608c5aa Update cmake list. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106348 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 23:12:10 +00:00
Evan Cheng 886459456c Thumb2 hazard recognizer. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106347 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 23:11:35 +00:00
Evan Cheng 86050dc8cc Allow ARM if-converter to be run after post allocation scheduling. 
- This fixed a number of bugs in if-converter, tail merging, and post-allocation
  scheduler. If-converter now runs branch folding / tail merging first to
  maximize if-conversion opportunities.
- Also changed the t2IT instruction slightly. It now defines the ITSTATE
  register which is read by instructions in the IT block.
- Added Thumb2 specific hazard recognizer to ensure the scheduler doesn't
  change the instruction ordering in the IT block (since IT mask has been
  finalized). It also ensures no other instructions can be scheduled between
  instructions in the IT block.

This is not yet enabled.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106344 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 23:09:54 +00:00
Evan Cheng 6a5e2832d0 Fix an inverted condition. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106330 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 22:17:13 +00:00
Evan Cheng a845706dc1 Fix cross initialization compilation error. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106324 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 22:01:37 +00:00
Evan Cheng a9934dc20a Teach iff-converter to properly count # of dups. It was not skipping over dbg_value's which resulted in non-duplicated instructions being deleted. rdar://8104384. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106323 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 21:52:57 +00:00
Evan Cheng 46df4eb46e Make post-ra scheduling, anti-dep breaking, and register scavenger (conservatively) aware of predicated instructions. This enables ARM to move if-conversion before post-ra scheduler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106091 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-16 07:35:02 +00:00
Evan Cheng 774bc882fd - Do away with SimpleHazardRecognizer.h. It's not used and offers little value. 
- Rename ExactHazardRecognizer to PostRAHazardRecognizer and move its header to include to allow targets to extend it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105959 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-14 21:06:53 +00:00
Evan Cheng 538ccb0d99 Avoid uncessary array copying. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105955 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-14 20:18:40 +00:00
Evan Cheng 729aab3dd3 Allow target to provide its own hazard recognizer to post-ra scheduler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105862 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-12 00:12:18 +00:00
Evan Cheng 44acc24117 Code formatting. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105861 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-12 00:11:53 +00:00
Evan Cheng 302ef834e0 Code refactoring, no functionality changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105775 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-10 02:09:31 +00:00
Evan Cheng aa4b5429ef Delete code that's not safe. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105774 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-10 02:08:20 +00:00
Evan Cheng 68fc2daf8f Allow target to place 2-address pass inserted copies in better spots. Thumb2 will use this to try to avoid breaking up IT blocks. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105745 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-09 19:26:01 +00:00
Evan Cheng 1d451dff63 Revert 105540, 105542, 105544, 105546, and 105548 to unbreak bootstrapping. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105740 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-09 18:59:43 +00:00
Evan Cheng 34aa423814 Typo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105677 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-09 03:49:12 +00:00
Evan Cheng d847124211 Thumb2 IT blocks are fairly expensive. When there are multiple selects using 
the same condition, it's important to make sure they are scheduled together
to avoid forming multiple IT blocks. I'm adding a pre-regalloc pass that forms
IT blocks early (by re-scheduling instructions and split basic blocks) to
attempt to fix this. This is not turned on by default since I am not sure this
is the right fix.

Another issue is llvm selects are modeled as two-address conditional moves.
This can be very bad when the copies before the conditional moves are not
coalesced away. Teach IT formation pass to move the copies above the IT block
(when legal) to avoid breaking the IT block.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105669 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-09 01:46:50 +00:00
Evan Cheng 2b4e727c6f Re-apply 105308 with fix. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105502 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-04 23:28:13 +00:00
Evan Cheng 9d709a8edb Enable machine cse of instructions which define physical registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105308 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-02 01:08:27 +00:00
Evan Cheng 701d4d309f Remove schedule-livein-copies. It's not being used. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105095 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-29 02:23:39 +00:00
Evan Cheng 9c044674e6 Fix PR7193: if sibling call address can take a register, make sure there are enough registers available by counting inreg arguments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105092 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-29 01:35:22 +00:00
Evan Cheng 82e0a1a1a8 Doh. Machine LICM is re-initializing the CSE map over and over. Patch by Anna Zaks. rdar://8037934. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105065 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-29 00:06:36 +00:00
Evan Cheng 046fa3f90a Fix some latency computation bugs: if the use is not a machine opcode do not just return zero. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105061 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-28 23:26:21 +00:00
Evan Cheng c10f5434b4 Schedule high latency instructions for latency reduction even if they are not vfp / NEON instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105060 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-28 23:25:23 +00:00
Evan Cheng 12616727c7 Use report_fatal_error, not llvm_unreachable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104899 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-27 23:45:31 +00:00
Evan Cheng 84f60b7359 llvm can't correctly support 'H', 'Q' and 'R' modifiers. Just mark it an error. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104891 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-27 22:08:38 +00:00
Evan Cheng 3946043a80 Avoid adding duplicate function live-in's. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104560 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-24 21:33:37 +00:00
Evan Cheng c7cf10c97e LR is in GPR, not tGPR even in Thumb1 mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104518 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-24 18:00:18 +00:00
Evan Cheng 2457f2c661 Implement @llvm.returnaddress. rdar://8015977. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104421 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-22 01:47:14 +00:00
Evan Cheng 835810bbf8 Allow machine cse to cse instructions which define physical registers. Controlled by option -machine-cse-phys-defs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104385 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 21:22:19 +00:00