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15538 Commits

Author SHA1 Message Date
Jim Grosbach
4adb182342 NEON VST3(single element from one lane) assembly parsing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148755 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-24 00:07:41 +00:00
Jim Grosbach
d7433e2873 NEON VST3(multiple 3-element structures) assembly parsing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148748 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-23 23:45:44 +00:00
Jim Grosbach
c387fc66bd NEON VLD3(multiple 3-element structures) assembly parsing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148745 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-23 23:20:46 +00:00
Devang Patel
f2d213745e Intel syntax: Robustify parsing of memory operand's displacement experssion. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148737 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-23 22:35:25 +00:00
Jim Grosbach
3a678af71d NEON VLD3 lane-indexed assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148734 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-23 21:53:26 +00:00
Rafael Espindola
16d7d437e0 Add support for .cfi_signal_frame. Fixes pr11762. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148733 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-23 21:51:52 +00:00
Jakob Stoklund Olesen
d0848a6398 Fix PR11829. PostRA LICM was too aggressive. 
This fixes a typo in r148589.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148724 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-23 21:01:15 +00:00
Devang Patel
3e08131185 Intel syntax: Parse memory operand with empty base reg, e.g. DWORD PTR [4*RDI] 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148721 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-23 20:20:06 +00:00
Jim Grosbach
8b31f95bdd Simplify some NEON assembly pseudo definitions. 
Let the generic token alias definitions handle the data subtype
suffices. We don't need explicit versions for each.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148718 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-23 19:39:08 +00:00
Devang Patel
7c64fe651a Intel syntax: Parse segment registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148712 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-23 18:31:58 +00:00
Evgeniy Stepanov
7908480e4c An option to selectively enable parts of ARM EHABI support. 
This change adds an new value to the --arm-enable-ehabi option that
disables emitting unwinding descriptors. This mode gives a working
backtrace() without the (currently broken) exception support.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148686 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-23 07:57:39 +00:00
Nick Lewycky
37abc488a0 Make Value::isDereferenceablePointer() handle unreachable code blocks. (This 
returns false in the event the computation feeding into the pointer is
unreachable, which maybe ought to be true -- but this is at least consistent
with undef->isDereferenceablePointer().) Fixes PR11825!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148671 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-23 00:05:17 +00:00
Anton Korobeynikov
4b4e62219b Add fused multiple+add instructions from VFPv4. 
Patch by Ana Pazos!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148658 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-22 12:07:33 +00:00
Devang Patel
1aea430b88 Intel syntax: Robustify register parsing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148591 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-20 22:32:05 +00:00
Andrew Trick
0041d4d447 Handle a corner case with IV chain collection with bailout instead of assert. 
Fixes PR11783: bad cast to AddRecExpr.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148572 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-20 21:23:40 +00:00
Andrew Trick
a44919ef45 Test case comments missing from my previous checkin. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148571 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-20 21:21:27 +00:00
Devang Patel
fdd3b30151 Intel syntax: Parse ... PTR [-8] 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148570 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-20 21:21:01 +00:00
Devang Patel
cf0e269d16 Intel syntax: For now, disable ambiguous JMP64pcrel32 for intel syntax. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148569 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-20 21:14:06 +00:00
Bob Wilson
1e9ccd68d4 ARM vector any_extends need to be selected to vmovl. <rdar://problem/10723651> 
We have patterns for vector sext and zext operations but were missing
anyext.  Without those patterns, codegen will fail when the selection DAG
has any_extend nodes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148568 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-20 20:59:56 +00:00
Jim Grosbach
6d56730ab8 VST2 four-register w/ update pseudos for fixed/register update. 
rdar://10724489

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148560 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-20 19:16:00 +00:00
Jim Grosbach
51222d1551 NEON use vmov.i32 to splat some f32 values into vectors. 
For bit patterns that aren't representable using the 8-bit floating point
representation for vmov.f32, but are representable via vmov.i32, treat
the .f32 syntax as an alias. Most importantly, this covers the case
'vmov.f32 Vd, #0.0'.

rdar://10616677

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148556 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-20 18:09:51 +00:00
Nick Lewycky
38b6d9dd22 Fix CountCodeReductionForAlloca to more accurately represent what SROA can and 
can't handle. Also don't produce non-zero results for things which won't be
transformed by SROA at all just because we saw the loads/stores before we saw
the use of the address.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148536 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-20 08:35:20 +00:00
Andrew Trick
b5c26ef9da SCEVExpander fixes. Affects LSR and indvars. 
LSR has gradually been improved to more aggressively reuse existing code, particularly existing phi cycles. This exposed problems with the SCEVExpander's sloppy treatment of its insertion point. I applied some rigor to the insertion point problem that will hopefully avoid an endless bug cycle in this area. Changes:

- Always used properlyDominates to check safe code hoisting.

- The insertion point provided to SCEV is now considered a lower bound. This is usually a block terminator or the use itself. Under no cirumstance may SCEVExpander insert below this point.

- LSR is reponsible for finding a "canonical" insertion point across expansion of different expressions.

- Robust logic to determine whether IV increments are in "expanded" form and/or can be safely hoisted above some insertion point.

Fixes PR11783: SCEVExpander assert.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148535 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-20 07:41:13 +00:00
Craig Topper
0e2037ba2b Add support for selecting 256-bit PALIGNR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148532 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-20 05:53:00 +00:00
Eli Friedman
a48678332b Remove a low-quality test which was failing on Windows; test/CodeGen/X86/sret.ll is a better test for the relevant behavior. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148526 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-20 02:06:40 +00:00
Eli Friedman
9a2478ac1a Support MSVC x86-32 sret convention. PR11688. Patch by Joe Groff. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148513 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-20 00:05:46 +00:00
Dan Gohman
0cdece4389 Set the "tail" flag on pattern-matched objc_storeStrong calls. 
rdar://10531041.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148490 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-19 19:14:36 +00:00
Devang Patel
a951f77ca3 Post process 'and', 'sub' instructions and select better encoding, if available. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148489 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-19 18:40:55 +00:00
Devang Patel
e60540f380 Intel syntax: There is no need to create unary expr for simple negative displacement. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148486 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-19 18:15:51 +00:00
Devang Patel
ac0f048602 Post process 'xor', 'or' and 'cmp' instructions and select better encoding, if available. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148485 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-19 17:53:25 +00:00
Evgeniy Stepanov
73dd8bbce3 Emit ARM EHABI unwinding instructions for 3 more Thumb instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148473 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-19 12:53:06 +00:00
Jim Grosbach
904b7be27e Add testcase. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148454 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-19 01:36:59 +00:00
Nick Lewycky
2faa5d2328 Space after punctuation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148451 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-19 01:13:47 +00:00
Nick Lewycky
22de16dc75 Add a TargetOption for disabling tail calls. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148442 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-19 00:34:10 +00:00
Jim Grosbach
0b4c673886 Thumb2 alternate syntax for LDR(literal) and friends. 
Explicit pc-relative syntax. For example, "ldrb r2, [pc, #-22]".

rdar://10250964

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148432 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-18 22:46:46 +00:00
Devang Patel
b8ba13f009 Process instructions after match to select alternative encoding which may be more desirable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148431 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-18 22:42:29 +00:00
Jim Grosbach
256ba4f42a Thumb2 relaxation for LDR(literal). 
If the fixup is out of range for the Thumb1 instruction, relax it
to the Thumb2 encoding instead.

rdar://10711829

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148424 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-18 21:54:16 +00:00
Dan Gohman
1dae3e965c Use llvm.global_ctors to locate global constructors instead 
of recognizing them by name.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148416 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-18 21:19:38 +00:00
Nadav Rotem
819026f2f8 Fix a bug in the type-legalization of vector integers. When we bitcast one vector type to another, we must not bitcast the result if one type is widened while the other is promoted. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148383 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-18 08:33:18 +00:00
Andrew Trick
97af768ccc Test case rename 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148344 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-17 22:27:45 +00:00
Jim Grosbach
8b9300b972 MC tweak symbol difference resolution for non-local symbols. 
When the non-local symbol in the expression is in the same fragment
as the second symbol, the assembler can still evaluate the expression
without needing a relocation.

For example, on ARM:
_foo:
	ldr lr, (_foo - 4)

rdar://10348687



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148341 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-17 22:14:39 +00:00
Jim Grosbach
283f1fff47 Tidy up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148339 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-17 22:03:42 +00:00
Devang Patel
2f8af1d643 Intel syntax: Fix parser match class to check memory operand size. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148338 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-17 21:48:03 +00:00
Nadav Rotem
ba05c91ed2 Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148337 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-17 21:44:01 +00:00
Devang Patel
6220fea2a8 Intel syntax: Parse "BYTE PTR [RDX + RCX]" 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148334 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-17 21:25:10 +00:00
Dan Gohman
2f6263c96a Add a new ObjC ARC optimization pass to eliminate unneeded 
autorelease push+pop pairs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148330 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-17 20:52:24 +00:00
Devang Patel
9a3d293cf3 Intel syntax: Do not unncessarily create plus expression for memory operand displacement. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148321 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-17 19:08:07 +00:00
Devang Patel
40bced0306 Intel syntax: Ignore mnemonic aliases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148316 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-17 18:30:45 +00:00
Eli Bendersky
aa2bb63d97 Remove "XFAIL: arm" from test/ExecutionEngine/test-return.ll 
The test passes on ARM bots



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148315 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-17 18:21:05 +00:00
Devang Patel
d37ad247cc Intel syntax: Robustify memory operand parsing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148312 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-17 18:00:18 +00:00