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3 Commits

Author SHA1 Message Date
Richard Sandiford
f9a5e40b90 Replace sra with srl if a single sign bit is required 
E.g. (and (sra (i32 x) 31) 2) -> (and (srl (i32 x) 30) 2).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192884 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-17 11:16:57 +00:00
Richard Sandiford
d77a7669ec [SystemZ] Handle extensions in RxSBG optimizations 
The input to an RxSBG operation can be narrower as long as the upper bits
are don't care.  This fixes a FIXME added in r192783.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192790 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-16 13:35:13 +00:00
Richard Sandiford
5d7e93c0d4 Handle (shl (anyext (shr ...))) in SimpilfyDemandedBits 
This is really an extension of the current (shl (shr ...)) -> shl optimization.
The main difference is that certain upper bits must also not be demanded.

The motivating examples are the first two in the testcase, which occur
in llvmpipe output.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192783 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-16 10:26:19 +00:00