6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-22 13:29:44 +00:00
Code Issues Projects Releases Wiki Activity
58,785 Commits 39 Branches 0 Tags
Commit Graph

375 Commits

Author SHA1 Message Date
Kevin Enderby
b46b03b36f Fixed the encoding problems of the crc32 instructions. All had the Operand size 
override prefix and only the r/m16 forms should have had that.  Also for variant
one, the AT&T syntax, added suffixes to all forms.  Also added the missing
64-bit form for 'CRC32 r64, r/m8'.  Plus added test cases for all forms and
tweaked one test case to add the needed suffixes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98980 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-19 20:04:42 +00:00
Chris Lattner
e3486a4c9a Now that tblgen can handle matching implicit defs of instructions 
to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking
two inputs (which have to be the same type) and *returning an i32*.
This is how the SDNodes get made in the graph, but we weren't able
to model it this way due to deficiencies in the pattern language.

Now we can change things like this:

 def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
-                  [(X86cmp RFP80:$lhs, RFP80:$rhs),
-                   (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i)
+                  [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>;

and fix terrible crimes like this:

-def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)),
+def : Pat<(X86cmp GR8:$src1, 0),
           (TEST8rr GR8:$src1, GR8:$src1)>;

This relies on matching the result of TEST8rr (which is EFLAGS, which is
an implicit def) to the result of X86cmp, an i32.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98903 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-19 00:01:11 +00:00
Chris Lattner
3d00578c95 fix a few more ambiguous types. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98531 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-15 05:53:30 +00:00
Chris Lattner
3485b51c4d fix some more ambiguous patterns, remove another nontemporalstore 
pattern which is broken (source and address swapped).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97958 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-08 18:57:56 +00:00
Chris Lattner
9a1ac4c107 remove a non-temporal store pattern which is not tested and 
could never have matched because the operand list was backwards.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97933 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-08 03:18:28 +00:00
Dan Gohman
874cadaf21 Implement XMM subregs. 
Extracting the low element of a vector is now done with EXTRACT_SUBREG,
and the zero-extension performed by load movss is now modeled with
SUBREG_TO_REG, and so on.

Register-to-register movss and movsd are no longer considered copies;
they are two-address instructions which insert a scalar into a vector.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97354 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-28 00:17:42 +00:00
Dan Gohman
bc9d98b52d The mayHaveSideEffects flag is no longer used. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97348 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-27 23:47:46 +00:00
Dan Gohman
e13709af60 Delete a bunch of redundant predicates. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97201 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-26 01:14:30 +00:00
Chris Lattner
6d9f86b773 remove a bunch of dead named arguments in input patterns, 
though some look dubious afaict, these are all ok.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96899 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-23 06:54:29 +00:00
Chris Lattner
1a7d087154 add a missing type cast. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96574 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-18 06:33:42 +00:00
David Greene
8939b0d8a9 Add support for emitting non-temporal stores for DAGs marked 
non-temporal.  Fix from r96241 for botched encoding of MOVNTDQ.

Add documentation for !nontemporal metadata.

Add a simpler movnt testcase.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96386 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-16 20:50:18 +00:00
Chris Lattner
cd10d14b4c revert r96241. It breaks two regression tests, isn't documented, 
and the testcase needs improvement.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96265 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-15 20:53:01 +00:00
David Greene
786da7dec2 Add support for emitting non-temporal stores for DAGs marked 
non-temporal.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96241 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-15 17:02:56 +00:00
Chris Lattner
eaca5fa8e6 Remove special cases for [LM]FENCE, MONITOR and MWAIT from 
encoder and decoder by using new MRM_ forms.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96048 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-12 23:54:57 +00:00
Nate Begeman
7cdba6d1f4 Add a missing pattern for movhps so that we get: 
movq	(%ecx,%edx,2), %xmm2
movhps	(%ecx,%eax,2), %xmm2

rather than:

movq     (%eax, %edx, 2), %xmm2		
movq     (%eax, %ebx, 2), %xmm3		
movlhps  %xmm3, %xmm2			

Testcase forthcoming.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95948 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-12 01:10:45 +00:00
Kevin Enderby
40fe18f66e Fix the encoding of the movntdqa X86 instruction. It was missing the 0x66 
prefix which is part of the opcode encoding.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95729 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-10 00:10:31 +00:00
Chris Lattner
be1778fea7 really kill off the last MRMInitReg inst, remove logic from encoder. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95437 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-05 21:34:18 +00:00
Chris Lattner
28c1d29b09 lower the last of the MRMInitReg instructions in MCInstLower. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95435 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-05 21:30:49 +00:00
David Greene
95eb2eeea6 Implement a feature (-vector-unaligned-mem) to allow targets to 
ignore alignment requirements for SIMD memory operands.  This
is useful on architectures like the AMD 10h that do not trap on
unaligned references if a status bit is twiddled at startup time.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93151 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-11 16:29:42 +00:00
Evan Cheng
b1f4981333 Remove target attribute break-sse-dep. Instead, do not fold load into sse partial update instructions unless optimizing for size. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91910 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-22 17:47:23 +00:00
Evan Cheng
400073d546 On recent Intel u-arch's, folding loads into some unary SSE instructions can 
be non-optimal. To be precise, we should avoid folding loads if the instructions
only update part of the destination register, and the non-updated part is not
needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these instructions breaks
the partial register dependency and it can improve performance. e.g.

movss (%rdi), %xmm0
cvtss2sd %xmm0, %xmm0

instead of
cvtss2sd (%rdi), %xmm0

An alternative method to break dependency is to clear the register first. e.g.
xorps %xmm0, %xmm0
cvtss2sd (%rdi), %xmm0


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91672 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-18 07:40:29 +00:00
Sean Callanan
108934c65d Instruction fixes, added instructions, and AsmString changes in the 
X86 instruction tables.

Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.

This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.

* X86*.td
	Removed tabs and fixed 80-line violations

* X86Instr64bit.td
	(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
		Added
	(CALL, CMOV) Added qualifiers
	(JMP) Added PC-relative jump instruction
	(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
		that it is 64-bit only (ambiguous since it has no
		REX prefix)
	(MOV) Added rr form going the other way, which is encoded
		differently
	(MOV) Changed immediates to offsets, which is more correct;
		also fixed MOV64o64a to have to a 64-bit offset
	(MOV) Fixed qualifiers
	(MOV) Added debug-register and condition-register moves
	(MOVZX) Added more forms
	(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
		(as with MOV) are encoded differently
	(ROL) Made REX.W required
	(BT) Uncommented mr form for disassembly only
	(CVT__2__) Added several missing non-intrinsic forms
	(LXADD, XCHG) Reordered operands to make more sense for
		MRMSrcMem
	(XCHG) Added register-to-register forms
	(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
	(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
		Added
* X86InstrFPStack.td
	(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
	 FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
	 FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
	 FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
	 FXRSTOR)
		Added
	(FCOM, FCOMP) Added qualifiers
	(FSTENV, FSAVE, FSTSW) Fixed opcode names
	(FNSTSW) Added implicit register operand
* X86InstrInfo.td
	(opaque512mem) Added for FXSAVE/FXRSTOR
	(offset8, offset16, offset32, offset64) Added for MOV
	(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
	 LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
	 LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
	 LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
	 CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
	 SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
	 VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
	 VMWRITE, VMXOFF, VMXON) Added
	(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
	(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
	 JGE, JLE, JG, JCXZ) Added 32-bit forms
	(MOV) Changed some immediate forms to offset forms
	(MOV) Added reversed reg-reg forms, which are encoded
		differently
	(MOV) Added debug-register and condition-register moves
	(CMOV) Added qualifiers
	(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
	(BT) Uncommented memory-register forms for disassembler
	(MOVSX, MOVZX) Added forms
	(XCHG, LXADD) Made operand order make sense for MRMSrcMem
	(XCHG) Added register-register forms
	(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
	(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
	change

* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
  qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91638 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-18 00:01:26 +00:00
Evan Cheng
c363094e04 Optimize splat of a scalar load into a shuffle of a vector load when it's legal. e.g. 
vector_shuffle (scalar_to_vector (i32 load (ptr + 4))), undef, <0, 0, 0, 0>
=>
vector_shuffle (v4i32 load ptr), undef, <1, 1, 1, 1>

iff ptr is 16-byte aligned (or can be made into 16-byte aligned).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90984 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-09 21:00:30 +00:00
Sean Callanan
b9e6b34e1e Recommitting PALIGNR shift width fixes. 
Thanks to Daniel Dunbar for fixing clang intrinsics:
  http://llvm.org/viewvc/llvm-project?view=rev&revision=89499


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89500 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-20 22:28:42 +00:00
Sean Callanan
1bbf6d1a6f Reverting PALIGNR fix until I figure out how this 
broke the Clang testsuite.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89495 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-20 22:09:28 +00:00
Sean Callanan
201dfa7432 Fixed PALIGNR to take 8-bit rotations in all cases. 
Also fixed the corresponding testcase, and the PALIGNR
  intrinsic (tested for correctness with llvm-gcc).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89491 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-20 21:40:28 +00:00
Evan Cheng
d15ac2fce3 Re-apply 89011. It's not to be blamed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89081 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-17 09:51:18 +00:00
Evan Cheng
6db07eac95 Revert 89011. Buildbot thinks it might be breaking stuff. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89076 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-17 09:20:28 +00:00
Evan Cheng
574186f8ad A few more instructions that should be marked re-materializable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89011 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-17 00:23:22 +00:00
Evan Cheng
600c043697 - Check memoperand alignment instead of checking stack alignment. Most load / store folding instructions are not referencing spill stack slots. 
- Mark MOVUPSrm re-materializable.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88974 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-16 21:56:03 +00:00
Nate Begeman
0b10b91465 x86 vector shuffle cleanup/fixes: 
1. rename the movhp patfrag to movlhps, since thats what it actually matches
2. eliminate the bogus movhps load and store patterns, they were incorrect.  The load transforms are already handled (correctly) by shufps/unpack.
3. revert a recent test change to its correct form.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86415 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-07 23:17:15 +00:00
Eric Christopher
761411c21b Fix a couple of shuffle patterns to use movhlps instead 
of movhps as the constraint.  Changes optimizations so
update testcases as appropriate as well.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86360 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-07 08:45:53 +00:00
Dan Gohman
533297b58d Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a 
bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85517 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-29 18:10:34 +00:00
Evan Cheng
89321166da X86 palignr intrinsics immediate field is in bits. ISel must transform it into bytes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85379 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-28 06:30:34 +00:00
Nate Begeman
a09008bf6d Add support for matching shuffle patterns with palignr. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84459 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 02:17:23 +00:00
Dan Gohman
4a0b3e170d Add support for rematerializing FsFLD0SS and FsFLD0SD as constant-pool 
loads in order to reduce register pressure.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82470 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-21 18:30:38 +00:00
Sean Callanan
5ab9403bc2 Added a variety of floating-point and SSE instructions. 
All of these do not have patterns (they're for the
disassembler).

Many of the floating-point instructions will probably
be rolled into definitions that have patterns, and may
eventually be superseded by mdefs.  So I put them
together and left a comment.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81979 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-16 01:13:52 +00:00
Sean Callanan
47234e6d38 Fixed PCMPESTRM128 to have opcode 0x60 instead of 0x62, as specified by the 
Intel documentation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79554 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-20 18:24:27 +00:00
Eric Christopher
b120ab4057 Implement sse4.2 string/text processing instructions: 
Add patterns and instruction encoding information.
Add custom lowering to deal with hardwired return register of
uncertain type (xmm0).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79377 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-18 22:50:32 +00:00
Daniel Dunbar
7417b761c2 Add 'isCodeGenOnly' bit to Instruction .td records. 
- Used to mark fake instructions which don't correspond to an actual machine
   instruction (or are duplicates of a real instruction). This is to be used for
   "special cases" in the .td files, which should be ignored by things like the
   assembler and disassembler. We still need a good solution to handle pervasive
   duplication, like with the Int_ instructions.

 - Set the bit on fake "mov 0" style instructions, which allows turning an
   assembler matcher warning into a hard error.

 - -2 FIXMEs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78731 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-11 22:17:52 +00:00
Eric Christopher
027c2b11ea Fix up whitespace, remove commented out code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78600 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-10 21:48:58 +00:00
Daniel Dunbar
338825c192 llvm-mc/AsmMatcher: Change assembler parser match classes to their own record 
structure.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78581 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-10 18:41:10 +00:00
Daniel Dunbar
98164afb01 Extend comment on ParserMatchClass .td field, and add some missing 
classes for X86.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78524 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-09 06:00:04 +00:00
Eric Christopher
b4dc13cab7 Add crc32 instruction and intrinsics. Add a new class of prefix 
bytes for F2 0F 38 and propagate. Add a FIXME for a set
of possibilities which correspond to intrinsics already used.

New test.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78508 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-08 21:55:08 +00:00
Eric Christopher
44b93ff9ad Whitespace and 80-col cleanup. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77718 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-31 20:07:27 +00:00
Dan Gohman
a4714e025d Add a new register class to describe operands that can't be SP, 
due to x86 encoding restrictions. This is currently off by default
because it may cause code quality regressions. This is for PR4572.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77565 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-30 01:56:29 +00:00
Eric Christopher
71c6753d03 Add support for gcc __builtin_ia32_ptest{z,c,nzc} intrinsics. Lower 
to ptest instruction plus setcc. Revamp ptest instruction. Add test.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77407 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-29 00:28:05 +00:00
Eric Christopher
fbd6687cf1 Update insertps handling based on feedback. Move to a v4f32 style 
to support vector arguments and scalar arguments correctly. Update
lowering and fix comment to refer to pinsr* instead of insertps.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76921 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-24 00:33:09 +00:00
Eric Christopher
1e5cdea9d7 Support insertps via the intrinsic and add a couple of simple 
testcases to make sure it's being generated.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76843 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-23 02:22:41 +00:00
Eli Friedman
7e2242be71 Fix for PR2484: add an SSE1 pattern for a shuffle we normally prefer to 
handle with an SSE2 instruction.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73760 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-19 07:00:55 +00:00