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5 Commits

Author SHA1 Message Date
Kai Nacke
a1329ecb8e [mips] Add Octeon cnMips instructions seqi/snei and v3mulu/vmm0/vmulu. 
This patch adds the Octeon cnMips instructions seqi/snei and v3mulu/vmm0/vmulu.
It is only for the assembler. Test case is included.

Reviewed by: Daniel.Sanders@imgtec.com

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205631 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-04 16:21:59 +00:00
Kai Nacke
b96fc4a5ea [mips] Add more Octeon cnMips instructions 
Adds the instructions ext/ext32/cins/cins32.
It also changes pop/dpop to accept the two operand version and
adds a simple pattern to generate baddu.
Tests for the two operand versions (including baddu/dmul/dpop/pop)
and the code generation pattern for baddu are included.

Reviewed by: Daniel.Sanders@imgtec.com


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205449 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-02 18:40:43 +00:00
Kai Nacke
54c55edb0a [mips] Add Octeon cnMips instructions mtmX and mtpX 
Adds the Octeon cnMips instructions "load multiplier register MPLx" and "load product register Px".
Includes tests.

Reviews by: Daniel.Sanders@imgtec.com

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205343 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-01 18:35:26 +00:00
Matheus Almeida
8e7aa4be58 [mips] Use TwoOperandAliasConstraint for ArithLogicR instructions. 
This enables TableGen to generate an additional two operand matcher
for our ArithLogicR class of instructions (constituted by 3 register operands).
E.g.: and $1, $2 <=> and $1, $1, $2


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204826 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-26 16:09:43 +00:00
Kai Nacke
ebf9f0c6cb [MIPS] Add cpu octeon and some instructions 
The Octeon cpu from Cavium Networks is mips64r2 based and has an extended
instruction set. In order to utilize this with LLVM, a new cpu feature "octeon"
and a subtarget feature "cnmips" is added. A small set of new instructions
(baddu, dmul, pop, dpop, seq, sne) is also added. LLVM generates dmul, pop and
dpop instructions with option -mcpu=octeon or -mattr=+cnmips.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204337 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-20 11:51:58 +00:00