354 Commits

Author SHA1 Message Date
NAKAMURA Takumi
b720a3d15c Re-apply r211399, "Generate native unwind info on Win64" with a fix to ignore SEH pseudo ops in X86 JIT emitter.
--
This patch enables LLVM to emit Win64-native unwind info rather than
DWARF CFI.  It handles all corner cases (I hope), including stack
realignment.

Because the unwind info is not flexible enough to describe stack frames
with a gap of unknown size in the middle, such as the one caused by
stack realignment, I modified register spilling code to place all spills
into the fixed frame slots, so that they can be accessed relative to the
frame pointer.

Patch by Vadim Chugunov!

Reviewed By: rnk

Differential Revision: http://reviews.llvm.org/D4081

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211691 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-25 12:41:52 +00:00
Yaron Keren
c45bee91b8 Two small enhancements for the JIT.
When JITting a large project such as Boost it's quite hard to figure out the problematic inline asm without debug location. This patch provides debug location printout before the JIT aborts due to inline asm. printDebugLoc() was exposed from MachineInstr.cpp and reused here.

If the JIT run with debug info, don't bomb on DBG_VALUE but ignore them.

http://reviews.llvm.org/D3416



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210201 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-04 17:35:28 +00:00
Craig Topper
c34a25d59d [C++] Use 'nullptr'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207394 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-28 04:05:08 +00:00
Craig Topper
c848b1bbcf [C++] Use 'nullptr'. Target edition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207197 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-25 05:30:21 +00:00
Chandler Carruth
42e8630239 [Modules] Fix potential ODR violations by sinking the DEBUG_TYPE
definition below all of the header #include lines, lib/Target/...
edition.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206842 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-22 02:41:26 +00:00
Craig Topper
f2c9fef815 [C++11] Add 'override' keyword to virtual methods that override their base class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203378 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-09 07:44:38 +00:00
Rafael Espindola
7d7d99622f Replace PROLOG_LABEL with a new CFI_INSTRUCTION.
The old system was fairly convoluted:
* A temporary label was created.
* A single PROLOG_LABEL was created with it.
* A few MCCFIInstructions were created with the same label.

The semantics were that the cfi instructions were mapped to the PROLOG_LABEL
via the temporary label. The output position was that of the PROLOG_LABEL.
The temporary label itself was used only for doing the mapping.

The new CFI_INSTRUCTION has a 1:1 mapping to MCCFIInstructions and points to
one by holding an index into the CFI instructions of this function.

I did consider removing MMI.getFrameInstructions completelly and having
CFI_INSTRUCTION own a MCCFIInstruction, but MCCFIInstructions have non
trivial constructors and destructors and are somewhat big, so the this setup
is probably better.

The net result is that we don't create temporary labels that are never used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203204 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-07 06:08:31 +00:00
Craig Topper
fa0cf99585 Remove special FP opcode maps and instead add enough MRM_XX formats to handle all the FP operations. This increases format by 1 bit, but decreases opcode map by 1 bit so the TSFlags size doesn't change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201649 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-19 08:25:02 +00:00
Craig Topper
82a644adf2 Remove A6/A7 opcode maps. They can all be handled with a TB map, opcode of 0xa6/0xa7, and adding MRM_C0/MRM_E0 forms. Removes 376K from the disassembler tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201641 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-19 05:34:21 +00:00
Craig Topper
ced2756280 Recommit r201059 and r201060 with hopefully a fix for its original failure.
Original commits messages:

Add MRMXr/MRMXm form to X86 for use by instructions which treat the 'reg' field of modrm byte as a don't care value. Will allow for simplification of disassembler code.

Simplify a bunch of code by removing the need for the x86 disassembler table builder to know about extended opcodes. The modrm forms are sufficient to convey the information.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201065 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-10 06:55:41 +00:00
Bob Wilson
70ff3e91f7 Revert r201059 and r201060.
r201059 appears to cause a crash in a bootstrapped build of clang. Craig
isn't available to look at it right now, so I'm reverting it while he
investigates.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201064 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-10 05:28:30 +00:00
Craig Topper
d8fdb19a7f Add MRMXr/MRMXm form to X86 for use by instructions which treat the 'reg' field of modrm byte as a don't care value. Will allow for simplification of disassembler code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201059 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-10 00:50:34 +00:00
Craig Topper
6b6dfa5c5a Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200626 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-02 09:25:09 +00:00
Craig Topper
1415ca1781 Merge HasVEXPrefix/HasEVEXPrefix/HasXOPPrefix into a 2-bit 'encoding' field in TSFlags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200624 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-02 07:08:01 +00:00
Craig Topper
f0b161d774 Separate x86 opcode maps and 0x66/0xf2/0xf3 prefixes from each other in the TSFlags. This greatly simplifies the switch statements in the disassembler tables and the code emitters.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200522 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-31 08:47:06 +00:00
Craig Topper
45b8e5fa49 Move REP out of the Prefix field of the X86 format. Give it its own bit. It had special handling anyway and this enables a future patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200520 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-31 07:00:55 +00:00
Craig Topper
8d67f8372b Move address override handling in X86CodeEmitter to a place where it works for VEX encoded instructions too. This allows 32-bit addressing to work in 64-bit mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200517 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-31 05:42:35 +00:00
Craig Topper
fab01c1908 Remove use of OpSize for populating VEX_PP field. A prefix encoding is now used instead. Simplify some other code. No functional changes intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199353 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 06:14:45 +00:00
Craig Topper
525ae45240 Separate the concept of 16-bit/32-bit operand size controlled by 0x66 prefix and the current mode from the concept of SSE instructions using 0x66 prefix as part of their encoding without being affected by the mode.
This should allow SSE instructions to be encoded correctly in 16-bit mode which r198586 probably broke.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199193 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-14 07:41:20 +00:00
Craig Topper
0fee6d9703 Remove SegOvrBits from X86 TSFlags since they weren't being used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198588 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-06 06:51:58 +00:00
Craig Topper
c46a29cd9c Add missing MRM_XX forms to the old JIT emitter for consistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198258 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-31 03:26:24 +00:00
Craig Topper
64f275b59c Remove MRMInitReg form now that it's last use is gone.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198257 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-31 03:19:03 +00:00
Craig Topper
f63c806e11 Change type of XOP flag in code emitters to a bool. Remove a some unneeded cases from switch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191632 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-29 08:33:34 +00:00
Craig Topper
bd0decae3c Add comments for XOPA map introduced with TBM instructions.a
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191630 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-29 06:31:18 +00:00
Yunzhong Gao
685707c28e Adding intrinsics to the llvm backend for TBM instruction set.
Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1750



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191539 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-27 18:38:42 +00:00
Craig Topper
5bdf397e25 Synchronize VEX JIT encoding code with the MCJIT version. Fix a bug in the MCJIT code where CurOp was being incremented even if the operand it was pointing at wasn't used. Maybe only matters if there are any EVEX_K instructions that aren't VEX_4V.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188868 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-21 05:57:45 +00:00
Nadav Rotem
ec7b5e9290 In LLVM FMA3 operands are dst, src1, src2, src3, however dst is not encoded as it is always src1. This was causing the encoding of the operands to be off by one.
Patch by Chris Bieneman.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188866 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-21 05:03:10 +00:00
Bill Wendling
1ce4985e01 Remove unused c'tor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183570 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-07 20:59:31 +00:00
Tim Northover
85c622d6b6 X86: change MOV64ri64i32 into MOV32ri64
The MOV64ri64i32 instruction required hacky MCInst lowering because it
was allocated as setting a GR64, but the eventual instruction ("movl")
only set a GR32. This converts it into a so-called "MOV32ri64" which
still accepts a (appropriate) 64-bit immediate but defines a GR32.
This is then converted to the full GR64 by a SUBREG_TO_REG operation,
thus keeping everyone happy.

This fixes a typo in the opcode field of the original patch, which
should make the legact JIT work again (& adds test for that problem).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183068 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-01 09:55:14 +00:00
Eric Christopher
34431085de Temporarily Revert "X86: change MOV64ri64i32 into MOV32ri64" as it
seems to have caused PR16192 and other JIT related failures.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183059 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-31 23:30:45 +00:00
Tim Northover
43887bf3e6 X86: change MOV64ri64i32 into MOV32ri64
The MOV64ri64i32 instruction required hacky MCInst lowering because it was
allocated as setting a GR64, but the eventual instruction ("movl") only set a
GR32. This converts it into a so-called "MOV32ri64" which still accepts a
(appropriate) 64-bit immediate but defines a GR32. This is then converted to
the full GR64 by a SUBREG_TO_REG operation, thus keeping everyone happy.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182991 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-31 09:57:13 +00:00
Michael Liao
02d2e61252 Add CLAC/STAC instruction encoding/decoding support
As these two instructions in AVX extension are privileged instructions for
special purpose, it's only expected to be used in inlined assembly.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179266 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-11 04:52:28 +00:00
Craig Topper
8647750dfb Add X86 code emitter support AVX encoded MRMDestReg instructions.
Previously we weren't skipping the VVVV encoded register. Based on patch by Michael Liao.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177221 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-16 03:44:31 +00:00
Craig Topper
fdf168fbc4 Fix the name of a variable to match its declaration. Fixes build failure from r177014.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177015 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14 07:47:43 +00:00
Craig Topper
9d3f3c5f40 Fix a bug in the calculation of the VEX.B bit for FMA4 rr with the VEX.W bit set. The VEX.B was being calculated from the wrong operand. Fixes at least some portion of PR14185.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177014 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14 07:40:52 +00:00
Eli Bendersky
d07c2a5fa1 Fix comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174390 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05 16:53:11 +00:00
Chandler Carruth
0b8c9a80f2 Move all of the header files which are involved in modelling the LLVM IR
into their new header subdirectory: include/llvm/IR. This matches the
directory structure of lib, and begins to correct a long standing point
of file layout clutter in LLVM.

There are still more header files to move here, but I wanted to handle
them in separate commits to make tracking what files make sense at each
layer easier.

The only really questionable files here are the target intrinsic
tablegen files. But that's a battle I'd rather not fight today.

I've updated both CMake and Makefile build systems (I think, and my
tests think, but I may have missed something).

I've also re-sorted the includes throughout the project. I'll be
committing updates to Clang, DragonEgg, and Polly momentarily.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171366 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-02 11:36:10 +00:00
Chandler Carruth
d04a8d4b33 Use the new script to sort the includes of every file under lib.
Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.

Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-03 16:50:05 +00:00
Micah Villmow
3574eca1b0 Move TargetData to DataLayout.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165402 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-08 16:38:25 +00:00
Michael Liao
7abf67a092 Add register encoding support in X86 backend
- Add 'HwEncoding' for X86 registers and call getEncodingValue() to
  retrieve their encoding values.
- This's the first step to adopt new scheme. Furthur revising is onging.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165241 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-04 19:50:43 +00:00
Craig Topper
8a312fb3aa Remove code for setting the VEX L-bit as a function of operand size from the code emitters and the disassembler table builder. Fix a couple instructions that were still missing VEX_L.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164204 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-19 06:37:45 +00:00
Craig Topper
96601ca332 Add a getName function to MachineFunction. Use it in places that previously did getFunction()->getName(). Remove includes of Function.h that are no longer needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162347 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-22 06:07:19 +00:00
Craig Topper
f654554ee0 Don't use implicit register operands to calculate L-bit for AVX instructions. Needed because super reg defs and kills are added as implicit operands on 128-bit instructions. Fixes PR13349. Patch by Jose Fonseca.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160543 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-20 07:03:46 +00:00
Craig Topper
5aba78bd80 Update GATHER instructions to support 2 read-write operands. Patch from myself and Manman Ren.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160110 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-12 06:52:41 +00:00
Elena Demikhovsky
177cf1e1a3 Added FMA3 Intel instructions.
I disabled FMA3 autodetection, since the result may differ from expected for some benchmarks.
I added tests for GodeGen and intrinsics.
I did not change llvm.fma.f32/64 - it may be done later.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157737 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-31 09:20:20 +00:00
Benjamin Kramer
77fc4b297a Port support for SSE4a extrq/insertq to the old jit code emitter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157685 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-30 09:13:55 +00:00
Craig Topper
82dd67a1c8 Fix indentation of wrapped line for readability. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157309 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-23 03:59:53 +00:00
Craig Topper
5084c6b0a2 Tidy up some spacing and inconsistent use of pre/post increment. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157122 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-19 19:14:18 +00:00
Craig Topper
769237bb92 Copy some AVX support from MCJIT to JIT. Maybe will fix PR12748.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157109 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-19 08:28:17 +00:00
Jakub Staszak
dca40aa911 Remove unneeded break.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155959 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-01 23:08:16 +00:00