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33 Commits

Author SHA1 Message Date
Daniel Dunbar
24ec2e5a72 [tests] Cleanup initialization of test suffixes. 
- Instead of setting the suffixes in a bunch of places, just set one master
   list in the top-level config. We now only modify the suffix list in a few
   suites that have one particular unique suffix (.ml, .mc, .yaml, .td, .py).

 - Aside from removing the need for a bunch of lit.local.cfg files, this enables
   4 tests that were inadvertently being skipped (one in
   Transforms/BranchFolding, a .s file each in DebugInfo/AArch64 and
   CodeGen/PowerPC, and one in CodeGen/SI which is now failing and has been
   XFAILED).

 - This commit also fixes a bunch of config files to use config.root instead of
   older copy-pasted code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188513 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-16 00:37:11 +00:00
Richard Osborne
589ddc9887 [XCore] Add LDAPB instructions. 
With the change the disassembler now supports the XCore ISA in its
entirety.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181155 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-05 13:36:53 +00:00
Richard Osborne
c601bd69d5 [XCore] Add BLRB instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181152 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-05 13:24:16 +00:00
Nico Rieck
ef1762b6a1 Use object file specific section type for initial text section 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179494 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-14 21:18:36 +00:00
Richard Osborne
e50faa754b [XCore] Add bru instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178783 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-04 20:05:35 +00:00
Richard Osborne
c6ff29713d [XCore] The RRegs register class is a superset of GRRegs. 
At the time when the XCore backend was added there were some issues with
with overlapping register classes but these all seem to be fixed now.
Describing the register classes correctly allow us to get rid of a
codegen only instruction (LDAWSP_lru6_RRegs) and it means we can
disassemble ru6 instructions that use registers above r11.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178782 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-04 19:57:46 +00:00
Richard Osborne
6107bbbbdf [XCore] Check disassembly of the st8 instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178689 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-03 20:07:11 +00:00
Richard Osborne
ef6343347a [XCore] Update disassembler test to improve coverage of the instructions. 
Previously some instructions were unintentionally covered twice and
others were not covered at all.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178688 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-03 20:07:06 +00:00
Richard Osborne
8dc741e400 [XCore] Add missing 2r instructions. 
These instructions are not targeted by the compiler but it is needed for
the MC layer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175407 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-17 22:38:05 +00:00
Richard Osborne
763c858ede [XCore] Add TSETR instruction. 
This instruction is not targeted by the compiler but it is needed for the
MC layer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175406 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-17 22:32:41 +00:00
Richard Osborne
a970dde906 [XCore] Add missing u10 / lu10 instructions. 
These instructions are not targeted by the compiler but they are
needed for the MC layer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175404 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-17 20:44:48 +00:00
Richard Osborne
cbe6c88b68 [XCore] Add missing u6 / lu6 instructions. 
These instructions are not targeted by the compiler but they are
needed for the MC layer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175403 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-17 20:43:17 +00:00
Richard Osborne
970a479c02 [XCore] Add missing l2rus instructions. 
These instructions are not targeted by the compiler but they are
needed for the MC layer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173634 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-27 22:28:30 +00:00
Richard Osborne
b719d8b100 [XCore] Add missing l2r instructions. 
These instructions are not targeted by the compiler but they are
needed for the MC layer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173629 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-27 21:26:02 +00:00
Richard Osborne
9d2b1aef1b [XCore] Add missing 1r instructions. 
These instructions are not targeted by the compiler but they are
needed for the MC layer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173624 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-27 20:46:21 +00:00
Richard Osborne
f5e7e793f1 [XCore] Add missing 0r instructions. 
These instructions are not targeted by the compiler but they are
needed for the MC layer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173623 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-27 20:42:57 +00:00
Richard Osborne
c47bd9899b Add instruction encodings / disassembly support for l4r instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173501 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-25 21:55:32 +00:00
Richard Osborne
3b6a5eefe0 Add instruction encodings / disassembly support for l5r instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173479 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-25 20:20:07 +00:00
Richard Osborne
9e6a5a3746 Add instruction encodings / disassembly support for l6r instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173288 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-23 20:08:11 +00:00
Richard Osborne
0ec35ac4fc Add instruction encodings / disassembly support for u10 / lu10 instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173204 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-22 22:55:04 +00:00
Richard Osborne
8da5434346 Add instruction encodings / disassembly support for u6 / lu6 instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173086 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-21 20:44:17 +00:00
Richard Osborne
9b709f8b3f Add instruction encoding / disassembly support for ru6 / lru6 instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173085 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-21 20:42:16 +00:00
Richard Osborne
b853c415c6 Add instruction encodings / disassembly support for l2rus instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172987 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-20 18:51:15 +00:00
Richard Osborne
c78ec6b6bc Add instruction encodings / disassembly support for l3r instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172986 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-20 18:37:49 +00:00
Richard Osborne
a68c64fbb2 Add instruction encodings / disassembler support for 2rus instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172985 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-20 17:22:43 +00:00
Richard Osborne
62b8786d12 Add instruction encodings / disassembly support 3r instructions. 
It is not possible to distinguish 3r instructions from 2r / rus instructions
using only the fixed bits. Therefore if an instruction doesn't match the
2r / rus format try to decode it as a 3r instruction before returning Fail.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172984 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-20 17:18:47 +00:00
Richard Osborne
c47793c62c Add instruction encodings / disassembly support for l2r instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170345 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-17 16:28:02 +00:00
Richard Osborne
a839ffc323 Add instruction encodings for PEEK and ENDIN. 
Previously these were marked with the wrong format.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170334 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-17 14:23:54 +00:00
Richard Osborne
35150cbf41 Add instruction encodings / disassembly support for rus instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170330 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-17 13:50:04 +00:00
Richard Osborne
ff6114e872 Add instruction encodings for ZEXT and SEXT. 
Previously these were marked with the wrong format.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170327 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-17 13:20:37 +00:00
Richard Osborne
1ffe48a84b Add instruction encodings / disassembly support for 2r instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170323 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-17 12:29:31 +00:00
Richard Osborne
dd78daa199 Add instruction encodings / disassembly support for 0r instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170322 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-17 12:26:29 +00:00
Richard Osborne
e4e0089e45 Add tests for disassembly of 1r XCore instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170295 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-16 18:06:30 +00:00