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142 Commits

Author SHA1 Message Date
Jim Grosbach
8ba1474181 ARM: Better disassembly for pc-relative LDR. 
When the operand is a plain immediate rather than a label, print it
as [pc, #imm] like we do for the Thumb2 wide encoding variant.

rdar://12154503

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166991 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-10-30 01:04:51 +00:00
Kevin Enderby
e1d4a88134 Make branch heavy code for generating marked up disassembly simpler 
and easier to read by adding a couple helper functions.  Suggestion by
Chandler Carruth and seconded by Meador Inge!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166515 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-10-23 22:52:52 +00:00
Kevin Enderby
3ed0316f75 Add support for annotated disassembly output for X86 and arm. 
Per the October 12, 2012 Proposal for annotated disassembly output sent out by
Jim Grosbach this set of changes implements this for X86 and arm.  The llvm-mc
tool now has a -mdis option to produced the marked up disassembly and a couple
of small example test cases have been added.

rdar://11764962


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166445 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-10-22 22:31:46 +00:00
NAKAMURA Takumi
d15e2a0857 ARMInstPrinter.cpp: Fix a warning in -Asserts. [-Wunused-variable] 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164459 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-22 13:12:28 +00:00
NAKAMURA Takumi
2d67eac2e6 Whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164458 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-22 13:12:22 +00:00
Tim Northover
bb5174246b Fix edge cases of ARM shift operands in arith instructions. 
As before with load instructions, oddities like "asr #32", "rrx" could
be printed incorrectly.

Patch by Chris Lidbury.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164456 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-22 11:18:19 +00:00
Tim Northover
93c7c449a1 Fix the handling of edge cases in ARM shifted operands. 
This patch fixes load/store instructions to handle less common cases
like "asr #32", "rrx" properly throughout the MC layer.

Patch by Chris Lidbury.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164455 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-22 11:18:12 +00:00
Jiangning Liu
fd652df8b3 Fix #13035, a bug around Thumb instruction LDRD/STRD with negative #0 offset index issue. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161162 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-02 08:29:50 +00:00
Jiangning Liu
1fb27eccf5 Fix #13241, a bug around shift immediate operand for ARM instruction ADR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161159 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-02 08:13:13 +00:00
Jim Grosbach
7e99a60857 ARM: Define generic HINT instruction. 
The NOP, WFE, WFI, SEV and YIELD instructions are all hints w/
a different immediate value in bits [7,0]. Define a generic HINT
instruction and refactor NOP, WFI, WFI, SEV and YIELD to be
assembly aliases of that.

rdar://11600518

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158674 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-18 19:45:50 +00:00
Kevin Enderby
f49a4092bc Fix the encoding of the armv7m (MClass) for MSR registers other than aspr, 
iaspr, espr and xpsr which also needed to have 0b10 in their mask encoding bits.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158560 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-15 22:14:44 +00:00
Kevin Enderby
0fd4f3c8de Fix the encoding of the armv7m (MClass) for MSR APSR writes which was missing 
the 0b10 mask encoding bits.  Make MSR APSR writes without a _<bits> qualifier
an alias for MSR APSR_nzcvq even though ARM as deprecated it use.  Also add
support for suffixes (_nzcvq, _g, _nzcvqg) for APSR versions.  Some FIXMEs in
the code for better error checking when versions shouldn't be used.
rdar://11457025


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157019 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-17 22:18:01 +00:00
Silviu Baranga
ca3cd419a5 Fixed the LLVM ARM v7 assembler and instruction printer for 8-bit immediate offset addressing. The assembler and instruction printer were not properly handeling the #-0 immediate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156608 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-11 09:10:54 +00:00
Richard Barton
4d2f077df1 Refactor IT handling not to store the bottom bit of the condition code in the mask operand in the MCInst. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155700 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-27 08:42:59 +00:00
Kevin Enderby
6c22695c6d For ARM disassembly only print 32 unsigned bits for the address of branch 
targets so if the branch target has the high bit set it does not get printed as:
	 beq     0xffffffff8008c404


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154685 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-13 18:46:37 +00:00
Benjamin Kramer
c97ef618d2 Move getOpcodeName from the various target InstPrinters into the superclass MCInstPrinter. 
All implementations used the same code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153866 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-02 08:32:38 +00:00
Craig Topper
7c0b3c1fb6 Remove getInstructionName from MCInstPrinter implementations in favor of using the instruction name table from MCInstrInfo. Reduces static data in the InstPrinter implementations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153863 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-02 07:01:04 +00:00
Craig Topper
17463b3ef1 Make MCInstrInfo available to the MCInstPrinter. This will be used to remove getInstructionName and the static data it contains since the same tables are already in MCInstrInfo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153860 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-02 06:09:36 +00:00
Jim Grosbach
4d0983a4d7 ARM more NEON VLD/VST composite physical register refactoring. 
Register pair, all lanes subscripting.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152157 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-06 23:10:38 +00:00
Jim Grosbach
c0fc450f07 ARM refactor more NEON VLD/VST instructions to use composite physregs 
Register pair VLD1/VLD2 all-lanes instructions. Kill off more of the
pseudos as a result.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152150 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-06 22:01:44 +00:00
Jim Grosbach
bde1b2a5a8 Tidy up. Kill some dead code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152131 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-06 18:59:19 +00:00
Jim Grosbach
c3384c93c0 ARM Refactor VLD/VST spaced pair instructions. 
Use the new composite physical registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152063 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-05 21:43:40 +00:00
Jim Grosbach
28f08c93e7 ARM refactor away a bunch of VLD/VST pseudo instructions. 
With the new composite physical registers to represent arbitrary pairs
of DPR registers, we don't need the pseudo-registers anymore. Get rid of
a bunch of them that use DPR register pairs and just use the real
instructions directly instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152045 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-05 19:33:30 +00:00
Jim Grosbach
c6449b636f Make MCRegisterInfo available to the the MCInstPrinter. 
Used to allow context sensitive printing of super-register or sub-register
references.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152043 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-05 19:33:20 +00:00
Kevin Enderby
b0578512c7 Change ARMInstPrinter::printPredicateOperand() so it will not abort if it 
runs into the undefined 15 condition code value.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151844 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-01 22:13:02 +00:00
Ahmed Charles
b0934ab7d8 Remove dead code. Improve llvm_unreachable text. Simplify some control flow. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150918 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-19 11:37:01 +00:00
Jia Liu
31d157ae1a Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-18 12:03:15 +00:00
Craig Topper
bc2198133a Convert assert(0) to llvm_unreachable 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149961 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-07 02:50:20 +00:00
Jim Grosbach
a57a36abe7 NEON VLD4(all lanes) assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148884 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-25 00:01:08 +00:00
Jim Grosbach
5e59f7e15e NEON VLD3(all lanes) assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148882 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-24 23:47:04 +00:00
Jim Grosbach
8abe7e3364 NEON VLD4(multiple 4 element structures) assembly parsing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148762 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-24 00:43:17 +00:00
Jim Grosbach
c387fc66bd NEON VLD3(multiple 3-element structures) assembly parsing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148745 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-23 23:20:46 +00:00
Jim Grosbach
4050bc4cab ARM VFP assembly parsing and encoding for VCVT(float <--> fixed point). 
rdar://10558523

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147189 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-22 22:19:05 +00:00
Jim Grosbach
3471d4fbbd ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147025 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 00:38:54 +00:00
Jim Grosbach
2f196747f1 ARM assembly parsing and encoding support for LDRD(label). 
rdar://9932658

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146921 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-19 23:06:24 +00:00
Jim Grosbach
e90ac9bce9 ARM NEON VST2 assembly parsing and encoding. 
Work in progress. Parsing for non-writeback, single spaced register lists
works now. The rest have the representations better factored, but still
need more to be able to parse properly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146579 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 19:35:22 +00:00
Daniel Dunbar
4ab406d7fc LLVMBuild: Remove trailing newline, which irked me. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146409 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-12 19:48:00 +00:00
Jim Grosbach
13af222bab ARM parsing for VLD1 two register all lanes, no writeback. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145504 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-30 18:21:25 +00:00
Jim Grosbach
98b05a57b6 ARM parsing aliases for VLD1 single register all lanes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145464 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-30 01:09:44 +00:00
Daniel Dunbar
d782bae970 build/CMake: Finish removal of add_llvm_library_dependencies. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145420 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-29 19:25:30 +00:00
Benjamin Kramer
70be28a5ad Simplify some uses of utohexstr. 
As a side effect hex is printed lowercase instead of uppercase now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144013 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-07 21:00:59 +00:00
Daniel Dunbar
a3a2dfd4a2 build: Add initial cut at LLVMBuild.txt files. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143634 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-03 18:53:17 +00:00
Owen Anderson
81550dc0a8 Fix the issue that r143552 was trying to address the _right_ way. One-register lists are legal on LDM/STM instructions, but we should not print the PUSH/POP aliases when they appear. This fixes round tripping on this instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143557 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-02 18:03:14 +00:00
Jim Grosbach
b6310316db Assembly parsing for 4-register variant of VLD1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142682 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-21 20:35:01 +00:00
Jim Grosbach
cdcfa28056 Assembly parsing for 3-register variant of VLD1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142675 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-21 20:02:19 +00:00
Jim Grosbach
280dfad489 ARM VLD parsing and encoding. 
Next step in the ongoing saga of NEON load/store assmebly parsing. Handle
VLD1 instructions that take a two-register register list.

Adjust the instruction definitions to only have the single encoded register
as an operand. The super-register from the pseudo is kept as an implicit def,
so passes which come after pseudo-expansion still know that the instruction
defines the other subregs.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142670 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-21 18:54:25 +00:00
Jim Grosbach
293a5f69fa whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142657 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-21 16:56:40 +00:00
Jim Grosbach
862019c37f ARM VTBL (one register) assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142441 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 23:02:30 +00:00
Jim Grosbach
9b8f2a0b36 ARM parsing and encoding for the <option> form of LDC/STC instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141786 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-12 17:34:41 +00:00
Jim Grosbach
01208d56e8 80 columns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141781 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-12 16:36:01 +00:00