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159 Commits

Author SHA1 Message Date
Bob Wilson
f5fd499791 Fix a crash compiling 254.gap for Thumb2. The Thumb2 add/sub with 12-bit 
immediate instructions cannot set the condition codes, so they do not have
the extra cc_out operand.  We hit an assertion during tail duplication
because the instruction being duplicated had more operands that expected.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98001 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-08 22:56:15 +00:00
Johnny Chen
fb86d78a45 Trivial comment change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97776 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-05 01:45:46 +00:00
Johnny Chen
267124cff2 Drop the ".w" qualifier for t2UXTB16* instructions as there is no 16-bit version 
of either sxtb16 or uxtb16, and the unified syntax does not specify ".w".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97760 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-04 22:24:41 +00:00
Johnny Chen
0635fc5c27 Added 32-bit Thumb instructions for Preload Data (PLD, PLDW) and Preload 
Instruction (PLI) for disassembly only.

According to A8.6.120 PLI (immediate, literal), for example, different
instructions are generated for "pli [pc, #0]" and "pli [pc, #-0"].  The
disassembler solves it by mapping -0 (negative zero) to -1, -1 to -2, ..., etc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97731 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-04 17:40:44 +00:00
Johnny Chen
e54a3ef087 Added 32-bit Thumb instructions LDRT, LDRBT, LDRHT,,LDRSBT, LDRSHT, STRT, STRBT, 
and STRHT for disassembly only.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97655 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-03 18:45:36 +00:00
Johnny Chen
0f7866e796 Added 32-bit Thumb instructions t2NOP, t2YIELD, t2WFE, t2WFI, t2SEV, and t2DBG 
for disassembly only.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97632 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-03 02:09:43 +00:00
Evan Cheng
bc9d22c99a Eliminate unused instruction classes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97617 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-03 00:43:15 +00:00
Johnny Chen
a43398283d Added 32-bit Thumb instructions t2DMB variants, t2DSB variants, and t2ISBsy for 
disassembly only.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97614 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-03 00:16:28 +00:00
Johnny Chen
10a77e14a0 Added 32-bit Thumb instruction CLREX (Clear-Exclusive) for disassembly only. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97595 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-02 22:11:06 +00:00
Johnny Chen
b5031ad4c0 Removed the extra S from the multiclass def T2I_adde_sube_s_irs as well as from 
the opc string passed in, since it's a given from the class inheritance of T2sI.
The fixed the extra 's' in adcss & sbcss when disassembly printing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97582 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-02 19:38:59 +00:00
Johnny Chen
93042d1dc8 Added 32-bit Thumb instructions: CPS, SDIV, UDIV, SXTB16, SXTAB16, UXTAB16, SEL, 
SMMULR, SMMLAR, SMMLSR, TBB, TBH, and 16-bit Thumb instruction CPS for
disassembly only.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97573 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-02 18:14:57 +00:00
Johnny Chen
9d3acaa1a0 AL is an optional mnemonic extension for always, except in IT instructions. 
Add printMandatoryPredicateOperand() PrintMethod for IT predicate printing.

Ref: A8.3 Conditional execution

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97571 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-02 17:57:15 +00:00
Dan Gohman
bc9d98b52d The mayHaveSideEffects flag is no longer used. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97348 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-27 23:47:46 +00:00
Johnny Chen
adc7733a64 Added the follwoing 32-bit Thumb instructions for disassembly only: 
o Parallel addition and subtraction, signed/unsigned
o Miscellaneous operations: QADD, QDADD, QSUB, QDSUB
o Unsigned sum of absolute differences [and accumulate]: USAD8, USADA8
o Signed/Unsigned saturate: SSAT, SSAT16, USAT, USAT16
o Signed multiply accumulate long (halfwords): SMLAL<x><y>
o Signed multiply accumulate/subtract [long] (dual): SMLAD[x], SMLALD[X], SMLSD[X], SMLSLD[X]
o Signed dual multiply add/subtract [long]: SMUAD[X], SMUSD[X]


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97276 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-26 22:04:29 +00:00
Johnny Chen
6341c5a4c4 Added the following 32-bit Thumb instructions for disassembly only: SMC, RFE, 
and SRS.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97164 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-25 20:25:24 +00:00
Johnny Chen
ce6275fd2c Added the 32-bit Thumb instructions (BXJ) for disassembly only. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97163 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-25 19:05:29 +00:00
Johnny Chen
2333655ed0 Added the 32-bit Thumb instructions (MRS and MSR) for disassembly only. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97159 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-25 18:46:43 +00:00
Jim Grosbach
80dc116ce3 80 column cleanup 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96393 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-16 21:23:02 +00:00
Jim Grosbach
6417171026 Remove trailing whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96388 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-16 21:07:46 +00:00
Jim Grosbach
39be8fcfdc Update Thumb2 to not use CarryDefIsUnused or CarryDefIsUsed predicates, but 
to have the predicate on the pattern itself instead. Support for the new
ISel. Remove definitions of CarryDefIsUnused and CarryDefIsUsed since they are
no longer used anywhere.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96384 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-16 20:42:29 +00:00
Jim Grosbach
a87ded2695 tighten up eh.setjmp sequence a bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95603 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-08 23:22:00 +00:00
Johnny Chen
9474d550ff Added t2BFI (Bitfield Insert) entry for disassembler, with blank pattern field. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95112 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-02 19:31:58 +00:00
Jim Grosbach
d5d2baec26 Fix PR5694. The CMN instructions set the flags differently from CMP, so they 
cannot be directly interchanged for comparisons against negated values.
Disable the CMN instructions for the time being.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94119 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-22 00:08:13 +00:00
Evan Cheng
f609bb8466 Fix r93758. Use isel patterns instead of c++ selection code to select rbit and make sure we pick different instructions for ARM vs. Thumb2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93829 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-19 00:44:15 +00:00
Jim Grosbach
3482c8003a Patch by David Conrad: 
"On ARMv6T2 this turns cttz into rbit, clz instead of the 4 instruction
 sequence it is now."




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93758 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-18 19:58:49 +00:00
Johnny Chen
d248ffb7d5 Minor change, change the order of two "let Inst{...}" stmts within multiclass 
T2I_bin_ii12rs definition.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93006 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-08 17:41:33 +00:00
Johnny Chen
8314299161 Undo r92785, it caused test failure. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92796 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-05 22:37:28 +00:00
Johnny Chen
83f1136cfd Add Rt2 to the asm format string for 32-bit Thumb load/store register dual 
instructions.  Thumb does not have the restriction that t2 = t+1.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92785 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-05 21:51:46 +00:00
Jim Grosbach
587b072f23 Mark STREX* as earlyclobber for the success result register. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91555 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-16 19:44:06 +00:00
Johnny Chen
bbc71b2904 Add encoding bits for some Thumb instructions. Plus explicitly set the top two 
bytes of Inst to 0x0000 for the benefit of the Thumb decoder.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91496 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-16 02:32:54 +00:00
Johnny Chen
d68e119c0f Added encoding bits for the Thumb ISA. Initial checkin. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91434 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-15 17:24:14 +00:00
Jim Grosbach
7c03dbd8ed Add ARMv6 memory and sync barrier instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91329 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-14 21:24:16 +00:00
Jim Grosbach
a623f5a58d correct selection requirements for thumb2 vs. arm versions of the barrier intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91313 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-14 19:24:11 +00:00
Jim Grosbach
c219e4dd59 add Thumb2 atomic and memory barrier instruction definitions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91310 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-14 18:56:47 +00:00
Anton Korobeynikov
5cdc3a949a Materialize global addresses via movt/movw pair, this is always better 
than doing the same via constpool:
1. Load from constpool costs 3 cycles on A9, movt/movw pair - just 2.
2. Load from constpool might stall up to 300 cycles due to cache miss.
3. Movt/movw does not use load/store unit.
4. Less constpool entries => better compiler performance.

This is only enabled on ELF systems, since darwin does not have needed
relocations (yet).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89720 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-24 00:44:37 +00:00
Jim Grosbach
6935efcb66 80 column violations 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89718 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-24 00:20:27 +00:00
Jim Grosbach
15e6ef886d fold immediate of a + Const into the user as a subtract if it can fit as a negated two-part immediate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89694 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-23 20:35:53 +00:00
Evan Cheng
4aedb61d03 Remat VLDRD from constpool. Clean up some instruction property specifications. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89478 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-20 19:57:15 +00:00
Evan Cheng
b9803a8fa6 - Add pseudo instructions tLDRpci_pic and t2LDRpci_pic which does a pc-relative 
load of a GV from constantpool and then add pc. It allows the code sequence to
  be rematerializable so it would be hoisted by machine licm.
- Add a late pass to break these pseudo instructions into a number of real
  instructions. Also move the code in Thumb2 IT pass that breaks up t2MOVi32imm
  to this pass. This is done before post regalloc scheduling to allow the
  scheduler to proper schedule these instructions. It also allow them to be
  if-converted and shrunk by later passes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86304 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-06 23:52:48 +00:00
Evan Cheng
5a1cd36019 Fix t2Int_eh_sjlj_setjmp. Immediate form of orr is a 32-bit instruction. So it should be 22 bytes instead of 20 bytes long. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85965 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-03 23:13:34 +00:00
Bob Wilson
907eebd5a6 Put BlockAddresses into ARM constant pools. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85824 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-02 20:59:23 +00:00
David Goodwin
2f54a2fd85 Fix schedule model for BFC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85809 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-02 17:28:36 +00:00
Evan Cheng
9eda68988e It's safe to remat t2LDRpci; Add PseudoSourceValue to load / store's to enable more machine licm. More changes coming. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85643 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-31 03:39:36 +00:00
Bob Wilson
ddb16df912 Add ARM codegen for indirect branches. 
clang/test/CodeGen/indirect-goto.c runs! (unoptimized)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85577 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-30 05:45:42 +00:00
Dan Gohman
533297b58d Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a 
bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85517 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-29 18:10:34 +00:00
Evan Cheng
699bebac4f Change Thumb1 and Thumb2 instructions to separate opcode from operands with a tab instead of a space. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85184 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 00:08:59 +00:00
Jim Grosbach
65b7f3af76 Improve handling of immediates by splitting 32-bit immediates into two 16-bit 
immediate operands when they will fit into the using instruction.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84778 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 20:44:34 +00:00
Evan Cheng
2095659a85 Match more patterns to movt. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84751 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 08:15:52 +00:00
Sandeep Patel
47eedaa8fa Add ARMv6T2 SBFX/UBFX instructions. Approved by Anton Korobeynikov. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84009 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-13 18:59:48 +00:00
Evan Cheng
0d92f5f768 Add hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq flags to ld / st multiple, 
ld / st pairs, etc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83197 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-01 08:22:27 +00:00