c8e41c5917
Fix a typo (the the => the)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160621 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-23 08:51:15 +00:00
fae96f17b4
Fix instruction description of VMOV (between two ARM core registers and two single-precision resiters) (and do it properly this time!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159989 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10 12:51:09 +00:00
270e3625b2
Revert r159938 (and r159945) to appease the buildbots.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159960 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-09 20:43:34 +00:00
83cfff6229
Oops - correct broken disassembly for VMOV
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159945 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-09 18:20:02 +00:00
2e7e34ba54
Fix instruction description of VMOV (between two ARM core registers and two single-precision resiters)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159938 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-09 16:41:33 +00:00
c8f2fcc9a3
Correct decoder for T1 conditional B encoding
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158055 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-06 09:12:53 +00:00
dd051a0414
ARMDisassembler.cpp: Fix utf8 char in comments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157292 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-22 21:47:02 +00:00
3610a15c35
Tweak to the fix in r156212, as with the change in removing the shift the
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SignExtend32<22>(Val<<1) also needs to change to SignExtend32<21>(Val) .
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156213 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-04 22:09:52 +00:00
ce734d5ffe
Fix a bug in the ARM disassembler for wide branch conditional instructions
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where the symbolic operand's displacement was incorrectly shifted left by 1.
rdar://11387046
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156212 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-04 22:02:27 +00:00
2d524b0765
Fix issues with the ARM bl and blx thumb instructions and the J1 and J2 bits
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for the assembler and disassembler. Which were not being set/read correctly
for offsets greater than 22 bits in some cases.
Changes to lib/Target/ARM/ARMAsmBackend.cpp from Gideon Myles!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156118 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-03 22:41:56 +00:00
b422d0b65e
Fixed disassembler for vstm/vldm ARM VFP instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156077 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-03 16:38:40 +00:00
bb32f1d545
ARM: Tweak tADDrSP definition for consistent operand order.
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Make the operand order of the instruction match that of the asm syntax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155747 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-27 23:51:33 +00:00
4d2f077df1
Refactor IT handling not to store the bottom bit of the condition code in the mask operand in the MCInst.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155700 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-27 08:42:59 +00:00
f4478f99dd
Refactor Thumb ITState handling in ARM Disassembler to more efficiently use its vector
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155439 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24 11:13:20 +00:00
35ee7d28a6
Added support for disassembling unpredictable swp/swpb ARM instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155004 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-18 14:18:57 +00:00
fa1ebc6abe
Added support for unpredictable mcrr/mcrr2/mrrc/mrrc2 ARM instruction in the disassembler. Since the upredicability conditions are complex, C++ code was added to handle them.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155001 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-18 13:12:50 +00:00
c5a2a33938
Fix ARM disassembly of VLD2 (single 2-element structure to all lanes)
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instructions with writebacks. And add test a case for all opcodes handed by
DecodeVLD2DupInstruction() in ARMDisassembler.cpp .
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154884 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-17 00:49:27 +00:00
2a7d3a9373
Fix a few more places in the ARM disassembler so that branches get
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symbolic operands added when using the C disassembler API.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154628 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-12 23:13:34 +00:00
b318cc16c9
Fixed a case of ARM disassembly getting an assert on a bad encoding
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of a VST instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154544 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-11 22:40:17 +00:00
a69da35c12
Fix ARM disassembly of VLD instructions with writebacks. And add test a case
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for all opcodes handed by DecodeVLDInstruction() in ARMDisassembler.cpp .
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154459 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-11 00:25:40 +00:00
75e3b7fb8f
ARMDisassembler: drop bogus dependency on ARMCodeGen
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And indirectly, a dependency on most of the core LLVM optimization
libraries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153957 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-03 15:48:14 +00:00
c89c744b69
Remove unnecessary llvm:: qualifications
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153500 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-27 07:21:54 +00:00
6fe310e155
Added soft fail checks for the disassembler when decoding some corner cases of the STRD, STRH, LDRD, LDRH, LDRSH and LDRSB instructions on ARM.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153252 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-22 14:14:49 +00:00
b7c2ed6664
Added soft fail cases for the disassembler when decoding LDRSBT, LDRHT or LDRSHT instruction on ARM
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153251 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-22 13:24:43 +00:00
f0586f08df
Fix ARM disassembly of VST1 and VST2 instructions with writeback. And add test
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case for all opcodes handed by DecodeVSTInstruction() in ARMDisassembler.cpp .
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153218 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-21 20:54:32 +00:00
5c062ad926
The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153089 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20 15:54:56 +00:00
b78ca42384
Use uint16_t to store registers and opcode in static tables in the target specific backends.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152537 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-11 07:16:55 +00:00
ff3164a189
Tidy up. Remove dead code that slipped into previous commit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152184 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 00:52:39 +00:00
4d0983a4d7
ARM more NEON VLD/VST composite physical register refactoring.
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Register pair, all lanes subscripting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152157 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06 23:10:38 +00:00
c0fc450f07
ARM refactor more NEON VLD/VST instructions to use composite physregs
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Register pair VLD1/VLD2 all-lanes instructions. Kill off more of the
pseudos as a result.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152150 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06 22:01:44 +00:00
158c8a49c2
Fix a bug in the ARM disassembly of the neon VLD2 all lanes instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152127 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06 18:33:12 +00:00
c3384c93c0
ARM Refactor VLD/VST spaced pair instructions.
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Use the new composite physical registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152063 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-05 21:43:40 +00:00
28f08c93e7
ARM refactor away a bunch of VLD/VST pseudo instructions.
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With the new composite physical registers to represent arbitrary pairs
of DPR registers, we don't need the pseudo-registers anymore. Get rid of
a bunch of them that use DPR register pairs and just use the real
instructions directly instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152045 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-05 19:33:30 +00:00
adef06a714
Make MemoryObject accessor members const again
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151687 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-29 01:09:06 +00:00
0943303d31
Fix the symbolic operand added for the C disassmbler API for the ARM bl
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thumb instruction. The PC adjustment is +4 in Thumb mode and +8 in ARM mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151530 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-27 18:15:15 +00:00
b80d571ea8
Updated the llvm-mc disassembler C API to support for the X86 target.
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rdar://10873652
As part of this I updated the llvm-mc disassembler C API to always call the
SymbolLookUp call back even if there is no getOpInfo call back. If there is a
getOpInfo call back that is tried first and then if that gets no information
then the SymbolLookUp is called. I also made the code more robust by
memset(3)'ing to zero the LLVMOpInfo1 struct before then setting
SymbolicOp.Value before for the call to getOpInfo. And also don't use any
values from the LLVMOpInfo1 struct if getOpInfo returns 0. And also don't
use any of the ReferenceType or ReferenceName values from SymbolLookUp if it
returns NULL. rdar://10873563 and rdar://10873683
For the X86 target also fixed bugs so the annotations get printed.
Also fixed a few places in the ARM target that was not producing symbolic
operands for some instructions. rdar://10878166
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151267 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-23 18:18:17 +00:00
31d157ae1a
Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-18 12:03:15 +00:00
88b6fc06db
Make the EDis tables const.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150304 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-11 14:51:07 +00:00
bc2198133a
Convert assert(0) to llvm_unreachable
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149961 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-07 02:50:20 +00:00
2ea93875b2
Enable streaming of bitcode
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This CL delays reading of function bodies from initial parse until
materialization, allowing overlap of compilation with bitcode download.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149918 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-06 22:30:29 +00:00
4d6ccb5f68
More dead code removal (using -Wunreachable-code)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148578 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20 21:51:11 +00:00
60d99a5278
ARM NEON VTBL/VTBX assembly parsing and encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146691 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15 22:27:11 +00:00
bb3a2e4d0d
ARM NEON refactor VST2 w/ writeback instructions.
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In addition to improving the representation, this adds support for assembly
parsing of these instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146588 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 21:32:11 +00:00
e90ac9bce9
ARM NEON VST2 assembly parsing and encoding.
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Work in progress. Parsing for non-writeback, single spaced register lists
works now. The rest have the representations better factored, but still
need more to be able to parse properly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146579 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 19:35:22 +00:00
4ab406d7fc
LLVMBuild: Remove trailing newline, which irked me.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146409 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-12 19:48:00 +00:00
a4e3c7fc4b
ARM assembly parsing and encoding for VLD2 with writeback.
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Refactor the instructions into fixed writeback and register-stride
writeback variants to simplify the offset operand (no more optional
register operand using reg0). This is a simpler representation and allows
the assembly parser to more easily handle these instructions.
Add tests for the instruction variants now supported.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146278 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 21:28:25 +00:00
7b8e121520
Remove unused variable
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145517 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30 19:53:11 +00:00
096334e25e
ARM parsing for VLD1 all lanes, with writeback.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145510 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30 19:35:44 +00:00
4c7edb3ad8
ARM assembly parsing and encoding for four-register VST1.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145450 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-29 22:58:48 +00:00
d5ca201891
ARM assembly parsing and encoding for three-register VST1.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145442 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-29 22:38:04 +00:00
