441 Commits

Author SHA1 Message Date
Reid Kleckner
2ab3b563da X86 MC: Handle instructions like fxsave that match multiple operand sizes
Instructions like 'fxsave' and control flow instructions like 'jne'
match any operand size. The loop I added to the Intel syntax matcher
assumed that using a different size would give a different instruction.
Now it handles the case where we get the same instruction for different
memory operand sizes.

This also allows us to remove the hack we had for unsized absolute
memory operands, because we can successfully match things like 'jnz'
without reporting ambiguity.  Removing this hack uncovered test case
involving 'fadd' that was ambiguous. The memory operand could have been
single or double precision.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216604 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-27 20:10:38 +00:00
Reid Kleckner
3c92309f0d MC: Split the x86 asm matcher implementations by dialect
The existing matcher has lots of AT&T assembly dialect assumptions baked
into it.  In particular, the hack for resolving the size of a memory
operand by appending the four most common suffixes doesn't work at all.
The Intel assembly dialect mnemonic table has ambiguous entries, so we
need to try matching multiple times with different operand sizes, since
that's the only way to choose different instruction variants.

This makes us more compatible with gas's implementation of Intel
assembly syntax.  MSVC assumes you want byte-sized operations for the
instructions that we reject as ambiguous.

Reviewed By: grosbach

Differential Revision: http://reviews.llvm.org/D4747

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216481 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-26 20:32:34 +00:00
Tim Northover
049ffbbdf2 TableGen: allow use of uint64_t for available features mask.
ARM in particular is getting dangerously close to exceeding 32 bits worth of
possible subtarget features. When this happens, various parts of MC start to
fail inexplicably as masks get truncated to "unsigned".

Mostly just refactoring at present, and there's probably no way to test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215887 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-18 11:49:42 +00:00
Reid Kleckner
41d6599bb1 MC X86: Accept ".att_syntax prefix" and diagnose noprefix
Fixes PR18916.  I don't think we need to implement support for either
hybrid syntax.  Nobody should write Intel assembly with '%' prefixes on
their registers or AT&T assembly without them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215031 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-06 23:21:13 +00:00
Reid Kleckner
ab418066a2 MS inline asm: Use memory constraints for functions instead of registers
This is consistent with how we parse them in a standalone .s file, and
inline assembly shouldn't differ.

This fixes errors about requiring more registers than available in
cases like this:
  void f();
  void __declspec(naked) g() {
    __asm pusha
    __asm call f
    __asm popa
    __asm ret
  }

There are no registers available to pass the address of 'f' into the asm
blob.  The asm should now directly call 'f'.

Tests will land in Clang shortly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214550 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-01 20:21:24 +00:00
Reid Kleckner
21e23ab6f9 MS inline asm: Fix null SMLoc when 'ptr' is missing after dword & co
This improves the diagnostics from the regular assembler, but more
importantly it fixes an assertion when parsing inline assembly.  Test
landing in Clang.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214468 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-01 00:59:22 +00:00
Reid Kleckner
0b3444cca9 X86 MC: Don't crash on empty memory operand parens
Instead, create an absolute memory operand.

Fixes PR20504.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214457 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-31 23:26:35 +00:00
Reid Kleckner
7895ae3135 X86 MC: Reject invalid segment registers before a memory operand colon
Previously we would execute unreachable during object emission.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214456 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-31 23:03:22 +00:00
Evgeniy Stepanov
8a78bb9836 [asan] Support x86 REP MOVS asm instrumentation.
Patch by Yuri Gorshenin.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214395 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-31 09:11:04 +00:00
Reid Kleckner
a749eccfed X86 asm parser: Avoid duplicating the list of aliased instructions
No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214364 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-31 00:07:33 +00:00
Reid Kleckner
7af08a4a9b X86 asm parser: Use a loop to disambiguate suffixes instead of copy paste
This works towards making the Intel syntax asm matcher use a completely
different disambiguation strategy.

No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214352 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-30 22:23:11 +00:00
Robert Khasanov
aac33cfc08 [SKX] Enabling SKX target and AVX512BW, AVX512DQ, AVX512VL features.
Enabling HasAVX512{DQ,BW,VL} predicates.
Adding VK2, VK4, VK32, VK64 masked register classes.
Adding new types (v64i8, v32i16) to VR512.
Extending calling conventions for new types (v64i8, v32i16)

Patch by Zinovy Nis <zinovy.y.nis@intel.com>
Reviewed by Elena Demikhovsky <elena.demikhovsky@intel.com>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213545 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-21 14:54:21 +00:00
Nico Weber
c1ef24ce39 ms inline asm: Don't add x86 segment registers to the clobber list.
Clang tries to check the clobber list but doesn't list segment registers in its
x86 register list. This fixes PR20343.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213303 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-17 20:24:55 +00:00
Ehsan Akhgari
ca57933f5e Add support for parsing the not operator in Microsoft inline assembly
This fixes http://llvm.org/PR20202

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212352 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-04 19:13:05 +00:00
Alp Toker
8dd8d5c2b2 Revert "Introduce a string_ostream string builder facilty"
Temporarily back out commits r211749, r211752 and r211754.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211814 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-26 22:52:05 +00:00
Alp Toker
2559070422 Introduce a string_ostream string builder facilty
string_ostream is a safe and efficient string builder that combines opaque
stack storage with a built-in ostream interface.

small_string_ostream<bytes> additionally permits an explicit stack storage size
other than the default 128 bytes to be provided. Beyond that, storage is
transferred to the heap.

This convenient class can be used in most places an
std::string+raw_string_ostream pair or SmallString<>+raw_svector_ostream pair
would previously have been used, in order to guarantee consistent access
without byte truncation.

The patch also converts much of LLVM to use the new facility. These changes
include several probable bug fixes for truncated output, a programming error
that's no longer possible with the new interface.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211749 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-26 00:00:48 +00:00
David Majnemer
f9ec8fe70c MS asm: Properly handle quoted symbol names
We would get confused by '@' characters in symbol names, we would
mistake the text following them for the variant kind.

When an identifier a string, the variant kind will never show up inside
of it.  Instead, check to see if there is a variant following the
string.

This fixes PR19965.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211249 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-19 01:25:43 +00:00
David Blaikie
c50f986b4d AsmMatchers: Use unique_ptr to manage ownership of MCParsedAsmOperand
I saw at least a memory leak or two from inspection (on probably
untested error paths) and r206991, which was the original inspiration
for this change.

I ran this idea by Jim Grosbach a few weeks ago & he was OK with it.
Since it's a basically mechanical patch that seemed sufficient - usual
post-commit review, revert, etc, as needed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210427 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-08 16:18:35 +00:00
Craig Topper
c848b1bbcf [C++] Use 'nullptr'. Target edition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207197 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-25 05:30:21 +00:00
Evgeniy Stepanov
23a4885f59 [asan] Use MCInstrInfo in inline asm instrumentation.
Patch by Yuri Gorshenin.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207115 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-24 13:29:34 +00:00
NAKAMURA Takumi
d5a7c3f2ec X86AsmParser.cpp: Fix memory leak at replacing movsd to movsl.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206991 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-23 14:51:35 +00:00
Evgeniy Stepanov
d6af41b2eb Create MCTargetOptions.
For now it contains a single flag, SanitizeAddress, which enables
AddressSanitizer instrumentation of inline assembly.

Patch by Yuri Gorshenin.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206971 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-23 11:16:03 +00:00
Evgeniy Stepanov
bf7cc396c6 AddressSanitizer instrumentation for MOV and MOVAPS.
This is an initial version of *Sanitizer instrumentation of assembly code.

Patch by Yuri Gorshenin.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203908 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-14 08:58:04 +00:00
Rafael Espindola
7e9df19d5f Use printable names to implement directional labels.
This changes the implementation of local directional labels to use a dedicated
map. With that it can then just use CreateTempSymbol, which is what the rest
of MC uses.

CreateTempSymbol doesn't do a great job at making sure the names are unique
(or being efficient when the names are not needed), but that should probably
be fixed in a followup patch.

This fixes pr18928.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203826 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-13 18:09:26 +00:00
Craig Topper
124c86ee4a [C++11] Add 'override' keyword to virtual methods that override their base class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203418 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-09 18:03:14 +00:00
Reid Kleckner
9035f6be4c MS asm: The initial dot in struct access is optional
Fixes PR18994.

Tests, once again, in that other repository.  =P

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203146 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-06 19:19:12 +00:00
Reid Kleckner
a9a43d01f2 MS asm: Attempt to parse variables followed by a bracketed displacement
This is required to include MSVC's <atomic> header, which we do now in
LLVM.

Tests forthcoming in Clang, since that's where we test semantic inline
asm changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202865 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-04 17:57:01 +00:00
Reid Kleckner
4e43e1e686 MC: Fix Intel assembly parser for [global + offset]
We were dropping the displacement on the floor if we also had some
immediate offset.

Should fix PR19033.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202774 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-04 00:33:17 +00:00
Evgeniy Stepanov
2c4b1c4853 X86Operand is extracted into individual header.
X86Operand is extracted into individual header, because it allows to create an
arbitrary memory operand and append it to MCInst. It'll be reused in X86 inline
assembly instrumentation.

Patch by Yuri Gorshenin.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202496 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-28 12:28:07 +00:00
Elena Demikhovsky
143df776e2 AVX-512: Fixed compilation issue
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201761 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-20 07:00:10 +00:00
Elena Demikhovsky
08316a11e4 AVX-512: Assembly parsing of broadcast semantic in AVX-512; imlemented by Nis Zinovy (zinovy.y.nis@intel.com)
Fixed truncate i32 to i1; a test will be provided in the next commit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201757 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-20 06:34:39 +00:00
Kevin Enderby
a2f4bb9077 Update the X86 assembler for .intel_syntax to accept
the << and >> bitwise operators.

rdar://15975725


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200896 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-06 01:21:15 +00:00
David Woodhouse
4396f5d9d2 Change MCStreamer EmitInstruction interface to take subtarget info
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200345 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-28 23:12:42 +00:00
Kevin Enderby
7772f9af13 Update the X86 assembler for .intel_syntax to produce an error for invalid base
registers in memory addresses that do not match the index register. As it does
for .att_syntax.

rdar://15887380


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199948 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-23 22:34:42 +00:00
Kevin Enderby
2f49a7b24b Update the X86 assembler for .intel_syntax to produce an error for invalid
scale factors in memory addresses. As it does for .att_syntax.

It was producing:
Assertion failed: (((Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8)) && "Invalid scale!"), function CreateMem, file /Volumes/SandBox/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp, line 1133.

rdar://14967214


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199942 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-23 21:52:41 +00:00
David Woodhouse
a1856c8aa7 [x86] Remove now-unused isSrcOp() and isDstOp() from X86AsmParser
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199810 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-22 15:08:58 +00:00
David Woodhouse
0ff018e500 [x86] Allow segment and address-size overrides for INS[BWLQ] (PR9385)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199809 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-22 15:08:55 +00:00
David Woodhouse
af588b9f0e [x86] Allow segment and address-size overrides for OUTS[BWLQ] (PR9385)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199808 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-22 15:08:49 +00:00
David Woodhouse
51cd16cbd5 [x86] Allow segment and address-size overrides for MOVS[BWLQ] (PR9385)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199807 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-22 15:08:42 +00:00
David Woodhouse
674140fc3e ]x86] Allow segment and address-size overrides for CMPS[BWLQ] (PR9385)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199806 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-22 15:08:36 +00:00
David Woodhouse
6abfcfe155 [x86] Allow address-size overrides for SCAS{8,16,32,64} (PR9385)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199805 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-22 15:08:27 +00:00
David Woodhouse
ccbfd5b18a [x86] Allow address-size overrides for STOS[BWLQ] (PR9385)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199804 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-22 15:08:21 +00:00
David Woodhouse
db9fa461d7 [x86] Allow segment and address-size overrides for LODS[BWLQ] (PR9385)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199803 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-22 15:08:08 +00:00
Craig Topper
50a2b1672d Teach x86 asm parser to handle 'opaque ptr' in Intel syntax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199477 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-17 07:44:10 +00:00
Craig Topper
9d0b786f72 Teach X86 asm parser to understand 'ZMMWORD PTR' in Intel syntax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199476 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-17 07:37:39 +00:00
Craig Topper
85026d9375 Allow x86 mov instructions to/from memory with absolute address to be encoded and disassembled with a segment override prefix. Fixes PR16962.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199364 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 07:36:58 +00:00
Kevin Enderby
96f3b25e8a Update the X86 assembler for .intel_syntax to accept
the | and & bitwise operators.

rdar://15570412


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199323 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-15 19:05:24 +00:00
Saleem Abdulrasool
b6e0946d40 correct target directive handling error handling
The target specific parser should return `false' if the target AsmParser handles
the directive, and `true' if the generic parser should handle the directive.
Many of the target specific directive handlers would `return Error' which does
not follow these semantics.  This change simply changes the target specific
routines to conform to the semantis of the ParseDirective correctly.

Conformance to the semantics improves diagnostics emitted for the invalid
directives.  X86 is taken as a sample to ensure that multiple diagnostics are
not presented for a single error.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199068 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-13 01:15:39 +00:00
David Woodhouse
ab5b9489e9 [x86] Make AsmParser validate registers for memory operands a bit better
We can't do a perfect job here. We *have* to allow (%dx) even in 64-bit
mode, for example, because it might be used for an unofficial form of
the in/out instructions. We actually want to do a better job of validation
*later*. Perhaps *instead* of doing it where we are at the moment.

But for now, doing what validation we *can* do in the place that the code
already has its validation, is an improvement.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198760 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-08 12:58:28 +00:00
Craig Topper
93c9401dff [x86] Add basic support for .code16
This is not really expected to work right yet. Mostly because we will
still emit the OpSize (0x66) prefix in all the wrong places, along with
a number of other corner cases. Those will all be fixed in the subsequent
commits.

Patch from David Woodhouse.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198584 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-06 04:55:54 +00:00