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85 Commits

Author SHA1 Message Date
Matt Arsenault
3987e532f7 R600: Fix i64 to i32 trunc on SI 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190091 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-05 19:41:10 +00:00
Tom Stellard
d08a930361 R600: Add support for vector local memory loads 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189226 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-26 15:06:04 +00:00
Tom Stellard
da25cd3e6d SelectionDAG: Use correct pointer size when lowering function arguments v2 
This adds minimal support to the SelectionDAG for handling address spaces
with different pointer sizes.  The SelectionDAG should now correctly
lower pointer function arguments to the correct size as well as generate
the correct code when lowering getelementptr.

This patch also updates the R600 DataLayout to use 32-bit pointers for
the local address space.

v2:
  - Add more helper functions to TargetLoweringBase
  - Use CHECK-LABEL for tests

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189221 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-26 15:05:36 +00:00
Benjamin Kramer
d0cad1f3ed R600: Allocate memoperand in the MachienFunction so it doesn't leak. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188555 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-16 14:48:09 +00:00
Tom Stellard
a41520cf9b R600/SI: Improve legalization of vector operations 
This should fix hangs in the OpenCL piglit tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188431 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-14 23:25:00 +00:00
Tom Stellard
e8e33f448e R600/SI: Replace v1i32 type with i32 in imageload and sample intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188430 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-14 23:24:53 +00:00
Tom Stellard
68db37b952 R600/SI: Convert v16i8 resource descriptors to i128 
Now that compute support is better on SI, we can't continue using v16i8
for descriptors since this is also a legal type in OpenCL.

This patch fixes numerous hangs with the piglit OpenCL test and since
we now use a target specific DAG node for LOAD_CONSTANT with the
correct MemOperandFlags, this should also fix:

https://bugs.freedesktop.org/show_bug.cgi?id=66805

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188429 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-14 23:24:45 +00:00
Tom Stellard
df4626ef15 R600/SI: Assign a register class to the $vaddr operand for MIMG instructions 
The previous code declared the operand as unknown:$vaddr, which made
it possible for scalar registers to be used instead of vector registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188425 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-14 23:24:17 +00:00
Niels Ole Salscheider
6e4dbcd115 R600/SI: FMA is faster than fmul and fadd for f64 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188136 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-10 10:38:54 +00:00
Niels Ole Salscheider
014773626d R600/SI: Implement fp32<->fp64 conversions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187988 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-08 16:06:15 +00:00
Tom Stellard
3492eefa4b R600/SI: Use VSrc_* register classes as the default classes for types 
Since the VSrc_* register classes contain both VGPRs and SGPRs, copies
that used be emitted by isel like this:

SGPR = COPY VGPR

Will now be emitted like this:

VSrC = COPY VGPR

This patch also adds a pass that tries to identify and fix situations where
a VGPR to SGPR copy may occur.  Hopefully, these changes will make it
impossible for the compiler to generate illegal VGPR to SGPR copies.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187831 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-06 23:08:28 +00:00
Tom Stellard
3406d882c0 R600/SI: Add more special cases for opcodes to ensureSRegLimit() 
Also factor out the register class lookup to its own function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187830 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-06 23:08:18 +00:00
Tom Stellard
8cd70d3a5b R600/SI: Custom lower i64 ZERO_EXTEND 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187580 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-01 15:23:26 +00:00
Tom Stellard
eb643b9b37 R600: Improve support for < 32-bit loads 
Reviewed-by: Vincent Lejeune <vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186921 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-23 01:48:35 +00:00
Tom Stellard
4e518fd941 R600/SI: Fix crash with VSELECT 
https://bugs.freedesktop.org/show_bug.cgi?id=66175

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186616 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-18 21:43:53 +00:00
Tom Stellard
cd0f245864 R600/SI: Add support for 64-bit loads 
https://bugs.freedesktop.org/show_bug.cgi?id=65873

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186339 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-15 19:00:09 +00:00
Tom Stellard
d2442c10f9 R600/SI: Add double precision fsub pattern for SI 
Patch by: Niels Ole Salscheider

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186179 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-12 18:15:08 +00:00
Tom Stellard
68e1328662 R600/SI: Add initial double precision support for SI 
Patch by: Niels Ole Salscheider

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186177 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-12 18:14:56 +00:00
Michel Danzer
a3e39dc705 R600/SI: Initial local memory support 
Enough for the radeonsi driver to use it for calculating derivatives.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186012 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-10 16:37:07 +00:00
Aaron Watry
f97c7fef52 R600: Consolidate expansion of v2i32/v4i32 ops for EG/SI 
By default, we expand these operations for both EG and SI. Move the
duplicated code into a common space for now. If the targets ever actually
implement these operations as instructions, we can override that in the relevant
target.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184848 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-25 13:55:57 +00:00
Aaron Watry
1842ec4d9f R600/SI: Expand xor v2i32/v4i32 
Add test cases for both vector sizes on SI and also add v2i32 test for EG.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184846 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-25 13:55:52 +00:00
Aaron Watry
41f3db569c R600/SI: Expand urem of v2i32/v4i32 for SI 
Also add lit test for both cases on SI, and v2i32 for evergreen.

Note: I followed the guidance of the v4i32 EG check... UREM produces really
complex code, so let's just check that the instruction was lowered
successfully.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184844 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-25 13:55:46 +00:00
Aaron Watry
e80978f9dd R600/SI: Expand udiv v[24]i32 for SI and v2i32 for EG 
Also add lit test for both cases on SI, and v2i32 for evergreen.

Note: I followed the guidance of the v4i32 EG check... UDIV produces really
complex code, so let's just check that the instruction was lowered
successfully.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184843 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-25 13:55:43 +00:00
Aaron Watry
c1fcf01d7f R600/SI: Expand ashr of v2i32/v4i32 for SI 
Also add lit test for both cases on SI, and v2i32 for evergreen.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184842 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-25 13:55:40 +00:00
Aaron Watry
61de9f83cb R600/SI: Expand srl of v2i32/v4i32 for SI 
Also add lit test for both cases on SI, and v2i32 for evergreen.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184841 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-25 13:55:37 +00:00
Aaron Watry
60e6dacd1c R600/SI: Expand shl of v2i32/v4i32 for SI 
Also add lit test for both cases on SI, and v2i32 for evergreen.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184840 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-25 13:55:32 +00:00
Aaron Watry
b8ce77752b R600/SI: Expand or of v2i32/v4i32 for SI 
Also add lit test for both cases on SI, and v2i32 for evergreen.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184839 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-25 13:55:29 +00:00
Aaron Watry
02ed261f7f R600/SI: Expand mul of v2i32/v4i32 for SI 
Also add lit test for both cases on SI, and v2i32 for evergreen.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184838 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-25 13:55:26 +00:00
Aaron Watry
e3599ca191 R600/SI: Expand and of v2i32/v4i32 for SI 
Also add lit test for both cases on SI, and v2i32 for evergreen.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184837 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-25 13:55:23 +00:00
Tom Stellard
73e44d8ae4 R600/SI: Report unaligned memory accesses as legal for > 32-bit types 
In reality, some unaligned memory accesses are legal for 32-bit types and
smaller too, but it all depends on the address space.  Allowing
unaligned loads/stores for > 32-bit types is mainly to prevent the
legalizer from splitting one load into multiple loads of smaller types.

https://bugs.freedesktop.org/show_bug.cgi?id=65873

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184822 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-25 02:39:35 +00:00
Tom Stellard
4010e43810 R600/SI: Expand sub for v2i32 and v4i32 for SI 
Also add a v2i32 test to the existing v4i32 test.

Patch by: Aaron Watry

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry<awatry@gmail.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184482 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-20 21:55:37 +00:00
Tom Stellard
fe91c515d7 R600/SI: Expand add for v2i32 and v4i32 
Also add SI tests to existing file and a v2i32 test for both
R600 and SI.

Patch by: Aaron Watry

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry <awatry@gmail.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184481 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-20 21:55:30 +00:00
Tom Stellard
3ff0abfaab R600: Rework subtarget info and remove AMDILDevice classes 
This should simplify the subtarget definitions and make it easier to
add new ones.

Reviewed-by: Vincent Lejeune <vljn@ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183566 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 20:37:48 +00:00
Bill Wendling
b5632b5b45 Don't cache the instruction and register info from the TargetMachine, because 
the internals of TargetMachine could change.

No functionality change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183561 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 20:28:55 +00:00
Tom Stellard
c170230b3a R600: Replace predicate loop with predicate function 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183351 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-05 23:39:50 +00:00
Tom Stellard
e5fcc0dee4 R600/SI: Add support for work item and work group intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183138 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-03 17:40:18 +00:00
Tom Stellard
e7397ee81a R600/SI: Add a calling convention for compute shaders 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183137 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-03 17:40:11 +00:00
Tom Stellard
e86f9d70ca R600/SI: Custom lower i64 sign_extend 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183136 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-03 17:40:03 +00:00
Tom Stellard
17e8ad67f0 R600/SI: Adjust some instructions' out register class after ISel 
This is necessary to avoid generating VGPR to SGPR copies in some
cases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183135 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-03 17:39:58 +00:00
Tom Stellard
b89a467559 R600/SI: Handle REG_SEQUENCE in fitsRegClass() 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183134 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-03 17:39:54 +00:00
Tom Stellard
051a28e0e8 R600/SI: Handle nodes with glue results correctly SITargetLowering::foldOperands() 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183133 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-03 17:39:50 +00:00
Tom Stellard
4956bc61e1 R600/SI: Rework MUBUF store instructions 
The lowering of stores is now mostly handled in the tablegen files.  No
more BUFFER_STORE nodes I generated during legalization.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183130 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-03 17:39:37 +00:00
Andrew Trick
ac6d9bec67 Track IR ordering of SelectionDAG nodes 2/4. 
Change SelectionDAG::getXXXNode() interfaces as well as call sites of
these functions to pass in SDLoc instead of DebugLoc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182703 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-25 02:42:55 +00:00
Benjamin Kramer
5c35290fa3 Move passes from namespace llvm into anonymous namespaces. Sort includes while there. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182594 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-23 17:10:37 +00:00
Benjamin Kramer
879b071bf5 R600: Hide symbols of implementation details. 
Also removes an unused function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182587 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-23 15:43:05 +00:00
Rafael Espindola
bbc45a3e28 Attempt to fix the mingw32 bot. 
This should hopefully fix
http://lab.llvm.org:8011/builders/clang-x86_64-darwin11-self-mingw32

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182446 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-22 02:30:47 +00:00
Tom Stellard
9bf4590aaa R600/SI: Make fitsRegClass() operands const 
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182282 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-20 15:02:01 +00:00
Matt Arsenault
225ed7069c Add LLVMContext argument to getSetCCResultType 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182180 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-18 00:21:46 +00:00
Christian Konig
e919678208 R600/SI: return undef instead of null for skipped arguments 
This is a candidate for the stable branch.

Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=64694

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182084 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-17 09:46:48 +00:00
Tom Stellard
ea73bd8a54 R600/SI: Handle arbitrary destination type in SITargetLowering::adjustWritemask 
Patch by: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181268 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-06 23:02:15 +00:00