20728 Commits

Author SHA1 Message Date
Matt Arsenault
1b00d91005 Vectorize starting from insertelements building a vector
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189233 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-26 17:56:35 +00:00
Tom Stellard
edd08f7428 SelectionDAG: Remove unnecessary uses of TargetLowering::getPointerTy()
If we have a binary operation like ISD:ADD, we can set the result type
equal to the result type of one of its operands rather than using
TargetLowering::getPointerTy().

Also, any use of DAG.getIntPtrConstant(C) as an operand for a binary
operation can be replaced with:
DAG.getConstant(C, OtherOperand.getValueType());

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189227 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-26 15:06:10 +00:00
Tom Stellard
d08a930361 R600: Add support for vector local memory loads
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189226 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-26 15:06:04 +00:00
Tom Stellard
a01cdea9c6 R600: Add support for i8 and i16 local memory loads
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189225 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-26 15:05:59 +00:00
Tom Stellard
c52565157d SelectionDAG: Use correct pointer size when splitting vector stores
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189224 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-26 15:05:55 +00:00
Tom Stellard
8e78012457 R600: Add support for i8 and i16 local memory stores
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189223 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-26 15:05:49 +00:00
Tom Stellard
7a0282daeb R600: Add support for v4i32 and v2i32 local stores
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189222 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-26 15:05:44 +00:00
Tom Stellard
da25cd3e6d SelectionDAG: Use correct pointer size when lowering function arguments v2
This adds minimal support to the SelectionDAG for handling address spaces
with different pointer sizes.  The SelectionDAG should now correctly
lower pointer function arguments to the correct size as well as generate
the correct code when lowering getelementptr.

This patch also updates the R600 DataLayout to use 32-bit pointers for
the local address space.

v2:
  - Add more helper functions to TargetLoweringBase
  - Use CHECK-LABEL for tests

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189221 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-26 15:05:36 +00:00
Elena Demikhovsky
92bfb54770 AVX-512: Added shuffle instructions -
VPSHUFD, VPERMILPS, VMOVDDUP, VMOVLHPS, VMOVHLPS, VSHUFPS, VALIGN
 single and double forms.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189215 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-26 12:45:35 +00:00
Vladimir Medic
e4bf77a128 This patch implements trap instructions for mips. The test cases are added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189213 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-26 10:02:40 +00:00
Bill Schmidt
3fad2bcd25 [PowerPC] Add fast-isel branch and compare selection.
First chunk of actual fast-isel selection code.  This handles direct
and indirect branches, as well as feeding compares for direct
branches.  PPCFastISel::PPCEmitIntExt() is just roughed in and will be
expanded in a future patch.  This also corrects a problem with
selection for constant pool entries in JIT mode or with small code
model.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189202 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-25 22:33:42 +00:00
Craig Topper
a4959f3f6e First round of fixes for the x86 fixes for the x86 move accumulator from/to memory offset instructions.
-Assembly parser now properly check the size of the memory operation specified in intel syntax. So 'mov word ptr [5], al' is no longer accepted.
-x86-32 disassembly of these instructions no longer sign extends the 32-bit address immediate based on size.
-Intel syntax printing prints the ptr size and places brackets around the address immediate.

Known remaining issues with these instructions:
-Segment override prefix is not supported. PR16962 and PR16961.
-Immediate size should be changed by address size prefix.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189201 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-25 22:23:38 +00:00
Venkatraman Govindaraju
2f17d0facf [Sparc] Add long double (f128) instructions to sparc backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189198 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-25 18:30:06 +00:00
Venkatraman Govindaraju
5ec8afa7cf [Sparc] Added V9's extra floating point registers and their aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189195 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-25 17:03:02 +00:00
Elena Demikhovsky
41f7baf181 AVX-512: added UNPACK instructions and tests for all-zero/all-ones vectors
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189189 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-25 12:54:30 +00:00
Reed Kotler
5e5c3069cd Start to add the LLVM builtins to the mips16 exclusion lists for fp.
I need to add the rest of these to the list or else to delay putting
out the actual stub until later in code generation when I know if
the external function ever got emitted

Resubmit this patch. The target triple needs to be added to the test so that 
clang does not tell the backend the wrong target when the host is BSD. There
is a clang bug in here somewhere that I need to track down. At Mips this
has been filed internally as a bug.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189186 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-25 02:40:25 +00:00
Shuxin Yang
0570be8404 Revert 189161
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189176 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-24 17:53:16 +00:00
Reed Kotler
cbbd1eeecb Start to add the builtind to the mips16 exclusion lists for fp.
I need to add the rest of these to the list or else to delay putting
out the actual stub until later in code generation when I know if
the external function ever got emitted.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189161 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-24 01:24:44 +00:00
Justin Holewinski
30632d2fbb [NVPTX] Re-enable assembly printing support for inline assembly
This support was removed by accident during the MC conversion

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189160 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-24 01:17:23 +00:00
Rafael Espindola
cb1339ebeb Update test to use rdrnd instead of rdrand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189146 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-23 20:49:02 +00:00
Rafael Espindola
9b14371830 Update tests to use sse4.2 instead of sse42.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189145 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-23 20:46:35 +00:00
Rafael Espindola
7cb1b5f5bf Replace more uses of sse41 with sse4.1.
llc using the host cpu features and *waning* on unknown features is probably
not a good thing :-(

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189144 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-23 20:39:19 +00:00
Rafael Espindola
56afd5e90b Update a test that I missed in the previous commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189143 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-23 20:27:02 +00:00
Rafael Espindola
4aa8bdaa46 Rename features to match what gcc and clang use.
There is no advantage in being different and using the same names simplifies
clang a bit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189141 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-23 20:21:34 +00:00
Peter Collingbourne
f3c0314310 DataFlowSanitizer: correctly combine labels in the case where they are equal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189133 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-23 18:45:06 +00:00
Joey Gouly
6cbb39e556 [ARM] Fix another ARM FastISel -verify-machineinstrs issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189109 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-23 15:20:56 +00:00
Evgeniy Stepanov
7c7b8e57f8 [msan] Fix handling of va_arg overflow area on x86_64.
The code was erroneously reading overflow area shadow from the TLS slot,
bypassing the local copy. Reading shadow directly from TLS is wrong, because
it can be overwritten by a nested vararg call, if that happens before va_start.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189104 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-23 12:11:00 +00:00
Joey Gouly
a0b2d332c1 [ARMv8] Add CodeGen for VMAXNM/VMINNM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189103 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-23 12:01:13 +00:00
Andrea Di Biagio
5768bb8d77 Add function attribute 'optnone'.
This function attribute indicates that the function is not optimized
by any optimization or code generator passes with the 
exception of interprocedural optimization passes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189101 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-23 11:53:55 +00:00
Richard Sandiford
a550b51bac [SystemZ] Add basic prefetch support
Just the instructions and intrinsics for now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189100 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-23 11:36:42 +00:00
Richard Sandiford
35c93e4e42 [SystemZ] Try reversing comparisons whose first operand is in memory
This allows us to make more use of the many compare reg,mem instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189099 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-23 11:27:19 +00:00
Richard Sandiford
65ddcfa8c1 [SystemZ] Prefer LHI;ST... over LAY;MV...
If we had a store of an integer to memory, and the integer and store size
were suitable for a form of MV..., we used MV... no matter what.  We could
then have sequences like:

    lay %r2, 0(%r3,%r4)
    mvi 0(%r2), 4

In these cases it seems better to force the constant into a register
and use a normal store:

    lhi %r2, 4
    stc %r2, 0(%r3, %r4)

since %r2 is more likely to be hoisted and is easier to rematerialize.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189098 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-23 11:18:53 +00:00
Richard Sandiford
a8a7099c18 Turn MipsOptimizeMathLibCalls into a target-independent scalar transform
...so that it can be used for z too.  Most of the code is the same.
The only real change is to use TargetTransformInfo to test when a sqrt
instruction is available.

The pass is opt-in because at the moment it only handles sqrt.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189097 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-23 10:27:02 +00:00
Tim Northover
287c84a0b4 ARM: make sure ARM-mode pseudo-inst requires IsARM
I'd forgotten that "Requires" blocks override rather than add to the
constraints, so my pseudo-instruction was being selected in Thumb mode leading
to nonsense instructions.

rdar://problem/14817358

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189096 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-23 10:16:39 +00:00
Daniel Dunbar
0a248bf714 [PR11606] ocaml bindings tests produce binaries in source dir
- Workaround for ocamlopt producing outputs adjacent to its source inputs, by
   having the tests copy the inputs into temporary directories in the output
   paths before building.

 - Patch by edward-san.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189081 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-23 00:55:32 +00:00
Michael Gottesman
7feaf762f4 Filecheckize some tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189079 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-23 00:23:28 +00:00
Michael Gottesman
e0e66b9dfa Update StripDeadDebugInfo to use DebugInfoFinder so that it is no longer stale to the point of not working and more resilient to debug info changes.
The current version of StripDeadDebugInfo became stale and no longer actually
worked since it was expecting an older version of debug info.

This patch updates it to use DebugInfoFinder and the modern DebugInfo classes as
much as possible to make it more redundent to such changes. Additionally, the
only place where that was avoided (the code where we replace the old sets with
the new), I call verify on the DIContextUnit implying that if the format changes
and my live set changes no longer make sense an assert will be hit. In order to
ensure that that occurs I have included a test case.

The actual stripping of the dead debug info follows the same strategy as was
used before in this class: find the live set and replace the old set in the
given compile unit (which may contain dead global variables/functions) with the
new live one.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189078 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-23 00:23:24 +00:00
Michael Gottesman
58a9b4388b [stack protector] Work around an issue with the BMOVPCB_CALL instruction on ARM by disabling does not return on __stack_chk_fail.
This is to fix the bots while I look to see if there is something I can do here.

rdar://14811848

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189076 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-22 23:45:24 +00:00
Bill Wendling
80075c482c Update to remove the no-frame-pointer-elim-non-leaf flag if it was set to 'false'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189068 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-22 21:28:54 +00:00
Bill Wendling
cec45be796 Fix some tests. The 'false' version just omits the attribute altogether.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189065 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-22 21:20:14 +00:00
Bill Wendling
b4be7f6b04 FileCheckize some tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189060 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-22 20:46:05 +00:00
Tom Stellard
344cfb4db4 R600/SI: Fix another case of illegal VGPR to SGPR copy
This fixes a crash in Unigine Tropics.

https://bugs.freedesktop.org/show_bug.cgi?id=68389

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189057 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-22 20:21:02 +00:00
Peter Collingbourne
054cec05b8 DataFlowSanitizer: Replace non-instrumented aliases of instrumented functions, and vice versa, with wrappers.
Differential Revision: http://llvm-reviews.chandlerc.com/D1442

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189054 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-22 20:08:15 +00:00
Peter Collingbourne
f1366c5524 DataFlowSanitizer: Prefix the name of each instrumented function with "dfs$".
DFSan changes the ABI of each function in the module.  This makes it possible
for a function with the native ABI to be called with the instrumented ABI,
or vice versa, thus possibly invoking undefined behavior.  A simple way
of statically detecting instances of this problem is to prepend the prefix
"dfs$" to the name of each instrumented-ABI function.

This will not catch every such problem; in particular function pointers passed
across the instrumented-native barrier cannot be used on the other side.
These problems could potentially be caught dynamically.

Differential Revision: http://llvm-reviews.chandlerc.com/D1373

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189052 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-22 20:08:08 +00:00
Manman Ren
094637408b [Debug Info Tests] Update testing cases.
A single metadata will not span multiple lines. This also helps me with
my script to automatic update the testing cases.
A debug info testing case should have a llvm.dbg.cu.
Do not use hard-coded id for debug nodes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189033 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-22 17:11:18 +00:00
Joey Gouly
35eab1db2f [ARMv8] Add CodeGen support for VSEL.
This uses the ARMcmov pattern that Tim cleaned up in r188995.

Thanks to Simon Tatham for his floating point help!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189024 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-22 15:29:11 +00:00
Mihai Popa
5f268555b9 Fix ARM vcvt encoding when the number of fractional bits is zero.
The instruction to convert between floating point and fixed point representations
takes an immediate operand for the number of fractional bits of the fixed point
value. ARMARM specifies that when that number of bits is zero, the assembler
should encode floating point/integer conversion instructions. 

This patch adds the necessary instruction aliases to achieve this behaviour.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189009 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-22 13:16:07 +00:00
Chandler Carruth
474be0d0f8 Teach the SLP vectorizer the correct way to check for consecutive access
using GEPs. Previously, it used a number of different heuristics for
analyzing the GEPs. Several of these were conservatively correct, but
failed to fall back to SCEV even when SCEV might have given a reasonable
answer. One was simply incorrect in how it was formulated.

There was good code already to recursively evaluate the constant offsets
in GEPs, look through pointer casts, etc. I gathered this into a form
code like the SLP code can use in a previous commit, which allows all of
this code to become quite simple.

There is some performance (compile time) concern here at first glance as
we're directly attempting to walk both pointers constant GEP chains.
However, a couple of thoughts:

1) The very common cases where there is a dynamic pointer, and a second
   pointer at a constant offset (usually a stride) from it, this code
   will actually not do any unnecessary work.

2) InstCombine and other passes work very hard to collapse constant
   GEPs, so it will be rare that we iterate here for a long time.

That said, if there remain performance problems here, there are some
obvious things that can improve the situation immensely. Doing
a vectorizer-pass-wide memoizer for each individual layer of pointer
values, their base values, and the constant offset is likely to be able
to completely remove redundant work and strictly limit the scaling of
the work to scrape these GEPs. Since this optimization was not done on
the prior version (which would still benefit from it), I've not done it
here. But if folks have benchmarks that slow down it should be straight
forward for them to add.

I've added a test case, but I'm not really confident of the amount of
testing done for different access patterns, strides, and pointer
manipulation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189007 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-22 12:45:17 +00:00
Joey Gouly
bad8d4ca59 [ARM] Constrain some register classes in EmitAtomicBinary64 so that
we pass these tests with -verify-machineinstrs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189006 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-22 12:19:24 +00:00
Logan Chien
7ddda4704c Fix ARM FastISel PIC function call.
The function call to external function should come with PLT relocation
type if the PIC relocation model is used.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189002 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-22 12:08:04 +00:00