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12566 Commits

Author SHA1 Message Date
Dan Gohman
4e6f7a0179 Remove a no-longer-necessary #include. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83697 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-10 00:36:09 +00:00
Dan Gohman
3731bc026c Replace X86's CanRematLoadWithDispOperand by calling the target-independent 
MachineInstr::isInvariantLoad instead, which has the benefit of being
more complete.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83696 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-10 00:34:18 +00:00
Dan Gohman
59ac57153b Mark the LDR instruction with isReMaterializable, as it is rematerializable 
when loading from an invariant memory location.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83688 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-09 23:28:27 +00:00
Dan Gohman
769b7f8953 Add a const qualifier. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83677 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-09 22:09:05 +00:00
Kevin Enderby
d7894f105a Added another bit of the ARM target assembler to llvm-mc to parse register 
lists.  Changed ARMAsmParser::MatchRegisterName to return -1 instead of 0 on
errors so 0-15 values could be returned as register numbers.  Also added the
rest of the arm register names to the currently hacked up version to allow more
testing.  Some changes to ARMAsmParser::ParseOperand to give different errors
for things not yet supported and some additions to the hacked
ARMAsmParser::MatchInstruction to allow more testing for now.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83673 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-09 21:12:28 +00:00
Dan Gohman
11596ed43c Fix the x86 test-shrink optimization so that it doesn't shrink comparisons 
when one of the bits being tested would end up being the sign bit in the
narrower type, and a signed comparison is being performed, since this would
change the result of the signed comparison. This fixes PR5132.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83670 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-09 20:35:19 +00:00
Dan Gohman
91e69c3715 Add basic infrastructure and x86 support for preserving MachineMemOperand 
information when unfolding memory references.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83656 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-09 18:10:05 +00:00
Bob Wilson
5631139a69 Add codegen support for NEON vst4lane intrinsics with 128-bit vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83600 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-09 00:01:36 +00:00
Bob Wilson
8cdb269686 Add codegen support for NEON vst3lane intrinsics with 128-bit vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83598 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-08 23:51:31 +00:00
Bob Wilson
c5c6edb74f Add codegen support for NEON vst2lane intrinsics with 128-bit vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83596 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-08 23:38:24 +00:00
Bob Wilson
62e053e5a1 Add codegen support for NEON vld4lane intrinsics with 128-bit vectors. 
Also fix some copy-and-paste errors in previous changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83590 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-08 22:53:57 +00:00
Bob Wilson
0bf7d998b4 Add codegen support for NEON vld3lane intrinsics with 128-bit vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83585 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-08 22:27:33 +00:00
Anton Korobeynikov
632606c724 Use lower16 / upper16 imm modifiers to asmprint 32-bit imms splitted via movt/movw pair. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83572 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-08 20:43:22 +00:00
Bob Wilson
30aea9d96e Add codegen support for NEON vld2lane intrinsics with 128-bit vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83568 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-08 18:56:10 +00:00
Bob Wilson
cd7e327cdf Clean up some unnecessary initializations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83566 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-08 18:52:56 +00:00
Bob Wilson
af4a891273 Clean up a comment (indentation was wrong). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83565 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-08 18:51:31 +00:00
Richard Osborne
bfa19bf4c2 Add missing names for the XCore specific LADD and LSUB nodes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83556 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-08 17:14:57 +00:00
Richard Osborne
c96c8e0e81 Add some peepholes for signed comparisons using ashr X, X, 32. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83549 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-08 15:38:17 +00:00
Bob Wilson
deb3141cf5 Add codegen support for NEON vst4 intrinsics with <1 x i64> vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83526 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-08 05:18:18 +00:00
Jim Grosbach
1f30dcbd8d Cleanup up unused R3LiveIn tracking. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83522 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-08 01:50:26 +00:00
Jim Grosbach
65c58daa8b Re-enable register scavenging in Thumb1 by default. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83521 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-08 01:46:59 +00:00
Bob Wilson
5adf60c03b Add codegen support for NEON vst3 intrinsics with <1 x i64> vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83518 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-08 00:28:28 +00:00
Bob Wilson
24e04c535f Add codegen support for NEON vst2 intrinsics with <1 x i64> vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83513 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-08 00:21:01 +00:00
Bob Wilson
0ea38bb939 Add codegen support for NEON vld4 intrinsics with <1 x i64> vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83508 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 23:54:04 +00:00
Bob Wilson
c67160c010 Add codegen support for NEON vld3 intrinsics with <1 x i64> vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83506 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 23:39:57 +00:00
Bob Wilson
a4288080e6 Add codegen support for NEON vld2 intrinsics with <1 x i64> vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83502 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 22:57:01 +00:00
Jim Grosbach
9f3a559dff reverting thumb1 scavenging default due to test failure while I figure out what's up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83501 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 22:49:41 +00:00
Dale Johannesen
5f3663e51d Fix handling of x86 'R' constraint. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83499 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 22:47:20 +00:00
Jim Grosbach
ec1434dd89 Enable thumb1 register scavenging by default. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83494 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 22:26:14 +00:00
Bob Wilson
b07c171624 Add some instruction encoding bits for NEON load/store instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83490 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 21:53:04 +00:00
Bob Wilson
63c9063434 Add codegen support for NEON vst4 intrinsics with 128-bit vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83486 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 20:49:18 +00:00
Bob Wilson
66a70639da Add codegen support for NEON vst3 intrinsics with 128-bit vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83484 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 20:30:08 +00:00
Bob Wilson
d285575f87 Add codegen support for NEON vst2 intrinsics with 128-bit vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83482 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 18:47:39 +00:00
Bob Wilson
7708c22baa Add codegen support for NEON vld4 intrinsics with 128-bit vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83479 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 18:09:32 +00:00
Kevin Enderby
99e6d4e839 Add another bit of the ARM target assembler to llvm-mc to parse registers 
with writeback, things like "sp!", etc.  Also added some more stuff to the
temporarily hacked methods ARMAsmParser::MatchRegisterName and
ARMAsmParser::MatchInstruction to allow more parser testing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83477 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 18:01:35 +00:00
Dan Gohman
e33f44cfc5 Replace TargetInstrInfo::isInvariantLoad and its target-specific 
implementations with a new MachineInstr::isInvariantLoad, which uses
MachineMemOperands and is target-independent. This brings MachineLICM
and other functionality to targets which previously lacked an
isInvariantLoad implementation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83475 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 17:38:06 +00:00
Bob Wilson
ff8952e8a9 Add codegen support for NEON vld3 intrinsics with 128-bit vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83471 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 17:24:55 +00:00
Bob Wilson
228c08b8dd Rearrange code for selecting vld2 intrinsics. No functionality change. 
This is just to be more consistent with the forthcoming code for vld3/4.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83470 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 17:23:09 +00:00
Jim Grosbach
b58f498f75 Add register-reuse to frame-index register scavenging. When a target uses 
a virtual register to eliminate a frame index, it can return that register
and the constant stored there to PEI to track. When scavenging to allocate
for those registers, PEI then tracks the last-used register and value, and
if it is still available and matches the value for the next index, reuses
the existing value rather and removes the re-materialization instructions.
Fancier tracking and adjustment of scavenger allocations to keep more
values live for longer is possible, but not yet implemented and would likely
be better done via a different, less special-purpose, approach to the
problem.

eliminateFrameIndex() is modified so the target implementations can return
the registers they wish to be tracked for reuse.

ARM Thumb1 implements and utilizes the new mechanism. All other targets are
simply modified to adjust for the changed eliminateFrameIndex() prototype.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83467 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 17:12:56 +00:00
Anton Korobeynikov
249fb339ad Add PseudoSourceValues for constpool stuff on ELF (Darwin should use something similar) 
and register spills.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83435 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 00:06:35 +00:00
Kevin Enderby
a7ba3a81c0 Added bits of the ARM target assembler to llvm-mc to parse some load instruction 
operands.  Some parsing of arm memory operands for preindexing and postindexing
forms including with register controled shifts.  This is a work in progress.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83424 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-06 22:26:42 +00:00
Bob Wilson
3bf12ab860 Add codegen support for NEON vld2 operations on quad registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83422 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-06 22:01:59 +00:00
Bob Wilson
349d82d400 Use copyRegToReg hook to copy registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83421 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-06 22:01:15 +00:00
Bob Wilson
a3e8bf8412 Fix a comment typo. 
Patch by Johnny Chen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83407 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-06 20:18:46 +00:00
Dan Gohman
e3cc3f3c84 Instead of printing unnecessary basic block labels as labels in 
verbose-asm mode, print comments instead. This eliminates a non-comment
difference between verbose-asm mode and non-verbose-asm mode.

Also, factor out the relevant code out of all the targets and into
target-independent code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83392 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-06 17:38:38 +00:00
Richard Osborne
f9416ea0cd Remove xs1b predicate since it is no longer needed to differentiate betweem 
xs1a and xs1b.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83383 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-06 16:17:57 +00:00
Richard Osborne
34bee6da7a Remove xs1a subtarget. xs1a is a preproduction device used in 
early development boards which is no longer supported in the
XMOS toolchain.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83381 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-06 16:01:09 +00:00
Richard Osborne
acfbb92824 Default to the xs1b subtarget 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83380 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-06 15:41:52 +00:00
Devang Patel
af0e272683 Update processDebugLoc() so that it can be used to process debug info before and after printing an instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83363 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-06 02:19:11 +00:00
Jim Grosbach
540b05d227 In Thumb1, the register scavenger is not always able to use an emergency 
spill slot. When frame references are via the frame pointer, they will be
negative, but Thumb1 load/store instructions only allow positive immediate
offsets. Instead, Thumb1 will spill to R12.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83336 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-05 22:30:23 +00:00