975651ab98
Add getTypeToExpandTo() which recursively walks TransformToType to determine
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the intrinsic type to expand to.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32558 91177308-0d34-0410-b5e6-96231b3b80d8
2006-12-13 20:52:00 +00:00
6586adfc1a
Update comments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32532 91177308-0d34-0410-b5e6-96231b3b80d8
2006-12-13 06:12:35 +00:00
b9d89c9ffb
Update comments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32531 91177308-0d34-0410-b5e6-96231b3b80d8
2006-12-13 06:09:03 +00:00
d27a258d2d
Cleaned setjmp/longjmp lowering interfaces. Now we're producing right
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code (both asm & cbe) for Mingw32 target.
Removed autoconf checks for underscored versions of setjmp/longjmp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32415 91177308-0d34-0410-b5e6-96231b3b80d8
2006-12-10 23:12:42 +00:00
5ff839fbab
Add a mechanism to specify whether a target supports a particular indexed load / store.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31597 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-09 18:56:43 +00:00
144d8f09e1
Rename ISD::MemOpAddrMode to ISD::MemIndexedMode
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31595 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-09 17:55:04 +00:00
d258efaf6e
getPostIndexedAddressParts change: passes in load/store instead of its loaded / stored VT.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31584 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-09 04:29:46 +00:00
a7bb6498fe
Added target hook for post-indexed memory ops transformation.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31499 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-07 09:04:16 +00:00
1a854be352
Rename
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31413 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-03 07:21:16 +00:00
24d9cf025d
Added a target specific hook to check whether / how a node can be transformed
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into a pair of base / offset nodes for pre-indexed load / store ops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31407 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-03 03:04:06 +00:00
a74b4a3ddc
generalize this api
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31365 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-02 01:39:10 +00:00
dba1aeedd8
Change the prototype for TargetLowering::isOperandValidForConstraint
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31318 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-31 19:40:43 +00:00
8b2794aeff
Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30945 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-13 21:14:26 +00:00
24446e253a
Merging ISD::LOAD and ISD::LOADX. Added LoadSDNode to represent load nodes.
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Chain and address ptr remains as operands. SrcValue, extending mode, extending
VT (or rather loaded VT before extension) are now instance variables of
LoadSDNode.
Introduce load / store addressing modes to represent pre- and post-indexed
load and store. Also added an additional operand offset that is only used in
post-indexed mode (i.e. base ptr += offset after load/store).
Added alignment info (not yet used) and isVolatile fields.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30843 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-09 20:55:20 +00:00
428e75eaef
Add support for targets to declare that they use a GOT
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30777 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-06 22:46:34 +00:00
c548428c5d
Combine ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD into ISD::LOADX. Add an
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extra operand to LOADX to specify the exact value extension type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30714 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-04 00:56:09 +00:00
2a0013f59f
add setJumpBufSize() and setJumpBufAlignment() to target-lowering.
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Call these from your backend to enjoy setjmp/longjmp goodness, see
lib/Target/IA64/IA64ISelLowering.cpp for an example
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30095 91177308-0d34-0410-b5e6-96231b3b80d8
2006-09-04 06:21:35 +00:00
232c910b8a
Start on my todo list
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28752 91177308-0d34-0410-b5e6-96231b3b80d8
2006-06-12 16:07:18 +00:00
19b7e0e0ca
For PR786:
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Minor tweaks in public headers and a few .cpp files so that LLVM can build
successfully with -pedantic and projects using LLVM with -pedantic don't
get warnings from LLVM. There's still more -pedantic warnings to fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28453 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-24 19:21:13 +00:00
7e399c14ab
Another typo. Pointed out by Nate Begeman.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28353 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-17 18:22:14 +00:00
5beaacc189
Fix a mis-leading comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28350 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-17 18:08:20 +00:00
6cacaee724
There is now a default impl of this method
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28336 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-16 22:52:11 +00:00
dae9cbe8d4
Move this code to a common place
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28329 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-16 17:42:15 +00:00
a0d513ba75
Add some new methods for computing sign bit information.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28144 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-06 09:26:22 +00:00
a69571c799
Refactor TargetMachine, pushing handling of TargetData into the target-specific subclasses. This has one caller-visible change: getTargetData() now returns a pointer instead of a reference.
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This fixes PR 759.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28074 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-03 01:29:57 +00:00
c313c66a88
Added a virtual method isVectorClearMaskLegal to TLI. It is similar to
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isShuffleMaskLegal, used to determine if it makes sense to turn a
"vector clear" (e.g. pand V, <0, -1, 0, -1> to a shuffle of the vector and
a zero vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27873 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-20 08:54:13 +00:00
b878151b1e
Provide a default impl of LowerArguments
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27605 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-12 16:21:12 +00:00
c45420ddd2
Move isShuffleLegal from TLI to Legalize.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27398 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-04 17:21:22 +00:00
e6bfffbae2
Allow targets to have fine grained control over which types various ops get
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promoted to, if they desire.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27389 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-04 00:25:10 +00:00
79227e2906
Modify the TargetLowering::getPackedTypeBreakdown method to also return the
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unpromoted element type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27273 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-31 00:46:36 +00:00
00cc494595
Add a method useful for decimating vectors.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27269 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-31 00:28:23 +00:00
ca6e8eafd2
Added a ValueType operand to isShuffleMaskLegal(). For now, x86 will not do
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64-bit vector shuffle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26964 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-22 22:07:06 +00:00
dc26e32ec7
Add some helper methods
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26882 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-20 00:55:52 +00:00
714554d707
Added a way for TargetLowering to specify what values can be used as the
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scale component of the target addressing mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26802 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-16 21:47:42 +00:00
30b37b5f29
Add LSR hooks.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26740 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-13 23:18:16 +00:00
1566d18fe2
custom lowered nodes are legal too
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26561 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-05 23:49:19 +00:00
33143dce15
Number of NodeTypes now exceeds 128.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26503 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-03 06:58:59 +00:00
00ffed0468
Add interfaces for targets to provide target-specific dag combiner optimizations.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26442 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-01 04:52:55 +00:00
bf57e1f456
Missing a cast previously.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26434 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-01 00:58:54 +00:00
5ee3e14127
Add C_Memory operand type
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26344 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-24 01:10:14 +00:00
410354fe0c
Make the LLVM headers "-ansi -pedantic -Wno-long-long" clean.
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Patch by Martin Partel!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26313 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-22 16:23:43 +00:00
1efa40f6a4
split register class handling from explicit physreg handling.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26308 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-22 00:56:39 +00:00
aba3b13fb3
Pass in a value type to getRegForInlineAsmConstraint, allowing targets to
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select different sets of registers depending on the type requested.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26304 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-21 23:10:29 +00:00
70804d3e14
Fix a nit sabre noticed
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26262 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-17 18:06:19 +00:00
368e18d56a
Rework the SelectionDAG-based implementations of SimplifyDemandedBits
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and ComputeMaskedBits to match the new improved versions in instcombine.
Tested against all of multisource/benchmarks on ppc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26238 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-16 21:11:51 +00:00
a03a5dc7ce
Rename maxStoresPerMemSet to maxStoresPerMemset, etc.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26174 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-14 08:38:30 +00:00
eac707f702
getConstraintType should be virtual.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26041 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-07 20:13:44 +00:00
c991cf58aa
Add some methods for inline asm support.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25950 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-04 02:12:09 +00:00
de99629e2a
Add a framework for eliminating instructions that produces undemanded bits.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25945 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-03 22:24:05 +00:00
cb0b555663
Clear the OpAction field before setting it. This allows a target to set
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an instruction operation action to Expand, then set it to Legal later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25812 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-30 06:09:03 +00:00
