Nate Begeman
b64af918cb
Fix casts of float to unsigned long
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Replace STDX (store 64 bit int indexed) with STFDX (store double indexed)
Fix latent bug in indexed load generation
Generate indexed loads and stores in many more cases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15626 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-10 20:42:36 +00:00
Misha Brukman
4ad7d1bee7
Use instruction formats as defined in the PowerPC ISA manual
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15577 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-09 17:24:04 +00:00
Misha Brukman
68f3459994
Remove unused opcodes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15447 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-03 20:23:44 +00:00
Misha Brukman
37dcae63eb
* Use simpler instruction templates to define instructions
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* Fix several extended opcodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15423 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-02 21:58:52 +00:00
Misha Brukman
28791dd17f
Separate instruction formats from instruction definitions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15414 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-02 16:54:54 +00:00
Misha Brukman
8c02c1cbb8
Renamed files:
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* PowerPCReg.td => PowerPCRegisterinfo.td
* PowerPCInstrs.td => PowerPCInstrInfo.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15295 91177308-0d34-0410-b5e6-96231b3b80d8
2004-07-27 23:29:16 +00:00
Misha Brukman
f228fa0580
Add COND_BRANCH pseudo instruction, patch by Nate Begeman.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15283 91177308-0d34-0410-b5e6-96231b3b80d8
2004-07-27 18:35:54 +00:00
Misha Brukman
53f567817c
MovePCtoLR (which is `bl' in disguise) modifies LR implicitly
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15272 91177308-0d34-0410-b5e6-96231b3b80d8
2004-07-27 17:15:05 +00:00
Misha Brukman
53d9a48855
Add SUBI instruction
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15077 91177308-0d34-0410-b5e6-96231b3b80d8
2004-07-21 15:53:04 +00:00
Misha Brukman
86ddcf9d4f
Differentiate between global and weak symbol loads
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15037 91177308-0d34-0410-b5e6-96231b3b80d8
2004-07-20 15:52:25 +00:00
Misha Brukman
2bf5438931
Add IMPLICIT_DEFS pseudo-instruction; patch by: Nate Begeman
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14895 91177308-0d34-0410-b5e6-96231b3b80d8
2004-07-16 20:33:41 +00:00
Misha Brukman
c661c3001c
* Coalesce the handy CALL* alias opcodes with the standard ones
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* Congregate more branch-and-link opcodes together
* Mark FP, CPR, and special registers as volatile across calls
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14511 91177308-0d34-0410-b5e6-96231b3b80d8
2004-06-30 22:00:45 +00:00
Misha Brukman
5fa2b028b8
* Use LA instead of LWZ for LoadLoAddr
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* Specify the isCall bit and caller-save registers for some call instrs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14501 91177308-0d34-0410-b5e6-96231b3b80d8
2004-06-29 23:37:36 +00:00
Misha Brukman
3905b57442
Fix the assembly opcode on LOADLoAddr, courtesy of Nate Begeman.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14470 91177308-0d34-0410-b5e6-96231b3b80d8
2004-06-28 18:27:08 +00:00
Misha Brukman
b2edb443e0
Set isBranch and isTerminator bits on all branch instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14469 91177308-0d34-0410-b5e6-96231b3b80d8
2004-06-28 18:23:35 +00:00
Misha Brukman
5dfe3a9c3b
Initial revision
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14283 91177308-0d34-0410-b5e6-96231b3b80d8
2004-06-21 16:55:25 +00:00
