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Author SHA1 Message Date
Ulrich Weigand
b64e2115de Do not consider a machine instruction that uses and defines the same 
physical register as candidate for common subexpression elimination
in MachineCSE.

This fixes a bug on PowerPC in MultiSource/Applications/oggenc/oggenc
caused by MachineCSE invalidly merging two separate DYNALLOC insns.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167855 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-13 18:40:58 +00:00