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265 Commits

Author SHA1 Message Date
Chris Lattner
3fc5b01d38 disable MaskedValueIsZero, ComputeMaskedBits, and SimplifyDemandedBits for 
i128 integers.  The 64-bit masks are not wide enough to represent the results.
These should be converted to APInt someday.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37169 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-17 18:19:23 +00:00
Evan Cheng
d60483ef99 Add target hook to specify block size limit for if-conversion. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37134 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-16 23:45:53 +00:00
Chris Lattner
75c7d2bd55 Allow i/s to match (gv+c). This fixes CodeGen/PowerPC/2007-05-03-InlineAsm-S-Constraint.ll 
and PR1382


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36672 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-03 16:54:34 +00:00
Chris Lattner
0a16a1f738 fix a pasto 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36242 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-18 03:01:40 +00:00
Chris Lattner
8c7d2d56bf Fix a bug in my previous patch, grabbing the shift amount width from the 
wrong operand.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36223 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-17 22:53:02 +00:00
Chris Lattner
895c4ab564 Fold (x << c1)>> c2 into a single shift if the bits shifted out aren't used. 
This compiles:
int baz(long long a) { return (short)(((int)(a >>24)) >> 9); }

into:
_baz:
        srwi r2, r3, 1
        extsh r3, r2
        blr

on PPC, instead of:
_baz:
        slwi r2, r3, 8
        srwi r2, r2, 9
        extsh r3, r2
        blr

GCC produces:
_baz:
        srwi r10,r4,24
        insrwi r10,r3,24,0
        srawi r9,r3,24
        srawi r3,r10,9
        extsh r3,r3
        blr

This implements CodeGen/PowerPC/shl_elim.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36221 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-17 21:14:16 +00:00
Anton Korobeynikov
bed2946a96 Removed tabs everywhere except autogenerated & external files. Add make 
target for tabs checking.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36146 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-16 18:10:23 +00:00
Chris Lattner
c2941779c3 Fix weirdness handling single element vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35941 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-12 04:44:28 +00:00
Chris Lattner
2b95fd67da remove dead target hooks. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35847 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-09 23:34:08 +00:00
Chris Lattner
b445d0cbb9 remove some dead target hooks, subsumed by isLegalAddressingMode 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35840 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-09 22:27:04 +00:00
Chris Lattner
d2f340b746 switch TL::getValueType to use MVT::getValueType. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35527 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-31 04:05:24 +00:00
Chris Lattner
1436bb657d add one addressing mode description hook to rule them all. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35520 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-30 23:14:50 +00:00
Evan Cheng
caaf69107e Remove isLegalAddressImmediate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35406 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-28 01:53:55 +00:00
Chris Lattner
c13dd1cf4c implement initial support for the silly X constraint. Testcase here: CodeGen/X86/2007-03-24-InlineAsmXConstraint.ll 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35327 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-25 04:35:41 +00:00
Chris Lattner
065421f99f Implement CodeGen/X86/2007-03-24-InlineAsmMultiRegConstraint.ll 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35324 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-25 02:18:14 +00:00
Chris Lattner
4234f57fa0 switch TargetLowering::getConstraintType to take the entire constraint, 
not just the first letter.  No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35322 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-25 02:14:49 +00:00
Dale Johannesen
fa4bce2b76 repair x86 performance, dejagnu problems from previous change 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35245 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-21 21:51:52 +00:00
Dale Johannesen
8e59e163db do not share old induction variables when this would result in invalid 
instructions (that would have to be split later)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35227 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-20 21:54:54 +00:00
Evan Cheng
14245a9d62 Added isLegalAddressExpression hook to test if the given expression can be 
folded into target addressing mode for the given type.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35121 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-16 08:42:32 +00:00
Evan Cheng
c289faf015 More flexible TargetLowering LSR hooks for testing whether an immediate is a legal target address immediate or scale. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35076 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-12 23:37:10 +00:00
Chris Lattner
6618039f9f initialize a instance variable 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34567 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-25 01:28:05 +00:00
Chris Lattner
01ca65b23e Fix CodeGen/Generic/2007-02-23-DAGCombine-Miscompile.ll and PR1219 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34551 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-24 02:09:29 +00:00
Jim Laskey
9bb3c93af2 Need to init. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34499 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-22 18:04:49 +00:00
Chris Lattner
9ff6ee85fe Implement i/n/s constraints correctly. This fixes 
test/CodeGen/PowerPC/2007-02-16-InlineAsmNConstraint.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34368 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-17 06:00:35 +00:00
Reid Spencer
9d6565a5b1 For PR1195: 
Rename PackedType -> VectorType, ConstantPacked -> ConstantVector, and
PackedTyID -> VectorTyID. No functional changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34293 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-15 02:26:10 +00:00
Chris Lattner
f839ce7d03 Fix PR1198, by adding initial i128 support. Patch by Dan Gohman. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34256 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-13 23:41:38 +00:00
Evan Cheng
fa1eb27b76 Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34065 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-08 22:13:59 +00:00
Chris Lattner
fea997aac5 Fit in 80 columns 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33745 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-01 04:55:59 +00:00
Evan Cheng
d385fd62cb Allow the target to override the ISD::CondCode that's to be used to test the 
result of the comparison libcall against zero.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33701 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-01-31 09:29:11 +00:00
Reid Spencer
02114aa0e5 Move a function out of line. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33158 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-01-12 23:30:31 +00:00
Evan Cheng
79cca507fe Minor fix. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33149 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-01-12 22:51:10 +00:00
Evan Cheng
56966225d1 Store default libgcc routine names and allow them to be redefined by target. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33105 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-01-12 02:11:51 +00:00
Anton Korobeynikov
d27a258d2d Cleaned setjmp/longjmp lowering interfaces. Now we're producing right 
code (both asm & cbe) for Mingw32 target.
Removed autoconf checks for underscored versions of setjmp/longjmp.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32415 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-12-10 23:12:42 +00:00
Evan Cheng
1a8f1fe676 Preliminary soft float support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32394 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-12-09 02:42:38 +00:00
Chris Lattner
3687c1a4d3 Fix the dag combiner bug corresponding to PR1014. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31943 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-27 21:50:02 +00:00
Evan Cheng
5ff839fbab Add a mechanism to specify whether a target supports a particular indexed load / store. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31597 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-09 18:56:43 +00:00
Reid Spencer
3ed469ccd7 For PR786: 
Turn on -Wunused and -Wno-unused-parameter. Clean up most of the resulting
fall out by removing unused variables. Remaining warnings have to do with
unused functions (I didn't want to delete code without review) and unused
variables in generated code. Maintainers should clean up the remaining
issues when they see them. All changes pass DejaGnu tests and Olden.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31380 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-02 20:25:50 +00:00
Chris Lattner
dba1aeedd8 Change the prototype for TargetLowering::isOperandValidForConstraint 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31318 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-31 19:40:43 +00:00
Evan Cheng
8b2794aeff Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30945 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-13 21:14:26 +00:00
Evan Cheng
2e49f090f9 Naming consistency. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30878 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-11 07:10:22 +00:00
Evan Cheng
466685d41a Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30844 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-09 20:57:25 +00:00
Chris Lattner
cf9668f23d initialize ivar 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30780 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-06 22:52:08 +00:00
Evan Cheng
c548428c5d Combine ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD into ISD::LOADX. Add an 
extra operand to LOADX to specify the exact value extension type.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30714 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-04 00:56:09 +00:00
Chris Lattner
7acf5f39fe Change the default to 0, which means 'default'. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30114 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-05 17:39:15 +00:00
Duraid Madina
0c9e0ff249 forgot this 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30097 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-04 07:44:11 +00:00
Evan Cheng
42f75a926a Fix a typo that causes 2006-07-07-ComputeMaskedBits.ll to fail. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29072 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-07 21:37:21 +00:00
Chris Lattner
c4fa603347 Port some bugfixes in shift handling from SimplifyDemandedBits over to 
ComputeMaskedBits.  DemandedMasks and KnownZero/One masks should never have
bits set out of the range of the base datatype.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28768 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-06-13 16:52:37 +00:00
Jim Laskey
9bfa2dcff6 TargetLowering::ComputeMaskedBits was not clearing reciprocal bits on shifts. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28765 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-06-13 13:08:58 +00:00
Andrew Lenharth
232c910b8a Start on my todo list 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28752 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-06-12 16:07:18 +00:00
Evan Cheng
7e399c14ab Another typo. Pointed out by Nate Begeman. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28353 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-17 18:22:14 +00:00