Vincent Lejeune
bb25a01d23
R600: Non vector only instruction can be scheduled on trans unit
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189980 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-04 19:53:46 +00:00
Tom Stellard
6b3f6a744a
Revert "R600: Non vector only instruction can be scheduled on trans unit"
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This reverts commit 98ce62780ehttps://llvm.org/svn/llvm-project/llvm/trunk@187526 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 20:43:27 +00:00
Vincent Lejeune
98ce62780e
R600: Non vector only instruction can be scheduled on trans unit
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187514 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 19:31:56 +00:00
Vincent Lejeune
a92f8ee2f3
R600: Don't mix LDS and non-LDS instructions in the same group
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There are a lot of restrictions on instruction groups that contain
LDS instructions, so for now we will be conservative and not packetize
anything else with them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187513 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 19:31:41 +00:00
Vincent Lejeune
f2cfef8172
R600: Do not predicated basic block with multiple alu clause
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Test is not included as it is several 1000 lines long.
To test this functionnality, a test case must generate at least 2 ALU clauses,
where an ALU clause is ~110 instructions long.
NOTE: This is a candidate for the stable branch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185943 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-09 15:03:33 +00:00
Vincent Lejeune
8f9fbd67c3
R600: Support schedule and packetization of trans-only inst
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185268 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-29 19:32:43 +00:00
Tom Stellard
e3d4cbc7d2
R600: Add local memory support via LDS
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Reviewed-by: Vincent Lejeune<vljn at ovi.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185162 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-28 15:47:08 +00:00
Tom Stellard
cedcfee405
R600: Add support for GROUP_BARRIER instruction
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Reviewed-by: Vincent Lejeune<vljn at ovi.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185161 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-28 15:46:59 +00:00
Tom Stellard
5e48a0e9ae
R600: Use new getNamedOperandIdx function generated by TableGen
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184880 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-25 21:22:18 +00:00
Vincent Lejeune
0c92287985
R600: 3 op instructions have no write bit but the result are store in PV
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183111 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-03 15:56:12 +00:00
Benjamin Kramer
5c35290fa3
Move passes from namespace llvm into anonymous namespaces. Sort includes while there.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182594 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-23 17:10:37 +00:00
Vincent Lejeune
4ed9917147
R600: Relax some vector constraints on Dot4.
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Dot4 now uses 8 scalar operands instead of 2 vectors one which allows register
coalescer to remove some unneeded COPY.
This patch also defines some structures/functions that can be used to handle
every vector instructions (CUBE, Cayman special instructions...) in a similar
fashion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182126 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-17 16:50:32 +00:00
Vincent Lejeune
25c209e9a2
R600: Some factorization
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182123 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-17 16:50:02 +00:00
Vincent Lejeune
152ebee8f3
R600: If previous bundle is dot4, PV valid chan is always X
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180959 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-02 21:52:55 +00:00
Vincent Lejeune
25f259cde2
R600: Packetize instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180760 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30 00:14:27 +00:00
