b8a80f03bf
Use i64 on a PPC64 machine
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41590 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-30 00:59:19 +00:00
48884cd80b
rename isOperandValidForConstraint to LowerAsmOperandForConstraint,
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changing the interface to allow for future changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41384 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-25 00:47:38 +00:00
66ffe6be0c
Vector fneg must be expanded into fsub -0.0, X.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40586 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-30 07:51:22 +00:00
36397f5034
Support for trampolines, except for X86 codegen which is
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still under discussion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40549 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-27 12:58:54 +00:00
75ce010f7b
Assert when TLS is not implemented.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39737 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-11 17:19:51 +00:00
532dc2e1f2
Change getCopyToParts and getCopyFromParts to always use target-endian
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register ordering, for both physical and virtual registers. Update the PPC
target lowering for calls to expect registers for the call result to
already be in target order.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38471 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-09 20:59:04 +00:00
ea859be53c
Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from
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TargetLowering to SelectionDAG so that they have more convenient
access to the current DAG, in preparation for the ValueType routines
being changed from standalone functions to members of SelectionDAG for
the pre-legalize vector type changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37704 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-22 14:59:07 +00:00
3ee774091b
describe an argument, hide it.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37650 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-19 05:46:06 +00:00
52387be1e0
If a function is vararg, never pass inreg arguments in registers. Thanks to
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Anton for half of this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37641 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-19 00:13:10 +00:00
51eaa86758
Rename MVT::getVectorBaseType to MVT::getVectorElementType.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37579 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-14 22:58:02 +00:00
f5135be3fc
Apply this patch:
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http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20070514/049845.html
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37240 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-18 23:21:46 +00:00
9f5d5783ec
fix some subtle inline asm selection issues
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37067 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-15 01:31:05 +00:00
7c7ba9d2d5
Fix a bug in PPCTargetLowering::isLegalAddressingMode, scales other than 0/1/2
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are always unsupported.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35835 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-09 22:10:05 +00:00
0111999a88
Starting implementation of the ELF32 ABI specification of varargs handling.
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LowerVASTART emits the right code if the subtarget is ELF32, the other intrinsics
(VAARG, VACOPY and VAEND) are not yet implemented.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35625 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-03 13:59:52 +00:00
ec58d9f9dd
The PPC64 ELF ABI is "intended to use the same structure layout and calling convention rules
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as the 64-bit PowerOpen ABI" (Reference http://www.linux-foundation.org/spec/ELF/ppc64/ ).
Change all ELF tests to ELF32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35624 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-03 12:35:28 +00:00
ef3c030e0e
The ELF ABI specifies F1-F8 registers as argument registers for double, not
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F1-F10. This affects only ELF, not MachO.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35622 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-03 10:27:07 +00:00
c9addb7488
implement the new addressing mode description hook.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35521 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-30 23:15:24 +00:00
1baa1971a6
"The C standards do say that "char" may either be a "signed char" or "unsigned
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char" and it is up to the compilers implementation or the platform which is
followed."
http://www.arm.linux.org.uk/docs/faqs/signedchar.php
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35382 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-27 16:33:08 +00:00
4234f57fa0
switch TargetLowering::getConstraintType to take the entire constraint,
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not just the first letter. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35322 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-25 02:14:49 +00:00
b2ec1cc6cb
Stack and register alignment of call arguments in the ELF ABI
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35083 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-13 15:02:46 +00:00
861939152d
More flexible TargetLowering LSR hooks for testing whether an immediate is a legal target address immediate or scale.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35074 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-12 23:29:01 +00:00
b9a7bea99c
Switch PPC return lower to use an autogenerated CC description.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34940 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-06 00:59:59 +00:00
43c6e7cd9b
Implemented the frameaddress intrinsic for PPC.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34787 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-01 13:11:38 +00:00
63f8fb1993
Differentiate between the MachO and the ELF ABI the CALL instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34667 91177308-0d34-0410-b5e6-96231b3b80d8
2007-02-27 13:01:19 +00:00
caddd44be7
always lower to RETFLAG, never leave it as just ret.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34639 91177308-0d34-0410-b5e6-96231b3b80d8
2007-02-26 19:44:02 +00:00
4ddf7a4ca6
no really, this is the right patch
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34605 91177308-0d34-0410-b5e6-96231b3b80d8
2007-02-25 20:01:40 +00:00
640c0ac01d
always promote float varargs to double.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34604 91177308-0d34-0410-b5e6-96231b3b80d8
2007-02-25 19:59:18 +00:00
9f0bc659c8
implement support for the linux/ppc function call ABI. Patch by
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Nicolas Geoffray!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34574 91177308-0d34-0410-b5e6-96231b3b80d8
2007-02-25 05:34:32 +00:00
2ad9f17fee
Simplify lowering and selection of exception ops.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34488 91177308-0d34-0410-b5e6-96231b3b80d8
2007-02-22 14:56:36 +00:00
62819f3144
Support to provide exception and selector registers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34482 91177308-0d34-0410-b5e6-96231b3b80d8
2007-02-21 22:54:50 +00:00
dee5a5a52c
Fix ixaddrs as well, allowing ppc64 to compile to:
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_test2:
li r2, 0
lis r3, 1
std r2, 9024(r3)
blr
instead of:
_test2:
lis r2, 1
li r3, 0
ori r2, r2, 9024
std r3, 0(r2)
blr
This implements CodeGen/PowerPC/LargeAbsoluteAddr.ll:test2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34373 91177308-0d34-0410-b5e6-96231b3b80d8
2007-02-17 06:57:26 +00:00
bc681d6af4
Compile test/CodeGen/PowerPC/LargeAbsoluteAddr.ll to:
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_test:
lis r2, 743
li r3, 0
stw r3, 32751(r2)
blr
instead of:
_test:
li r2, 0
stw r2, 32751(48693248)
blr
Implement support for ppc64 as well, allowing it to produce better code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34371 91177308-0d34-0410-b5e6-96231b3b80d8
2007-02-17 06:44:03 +00:00
bcc5f36765
Finish off bug 680, allowing targets to custom lower frame and return
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address nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33636 91177308-0d34-0410-b5e6-96231b3b80d8
2007-01-29 22:58:52 +00:00
b10308e440
Propagate changes from my local tree. This patch includes:
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1. New parameter attribute called 'inreg'. It has meaning "place this
parameter in registers, if possible". This is some generalization of
gcc's regparm(n) attribute. It's currently used only in X86-32 backend.
2. Completely rewritten CC handling/lowering code inside X86 backend.
Merged stdcall + c CCs and fastcall + fast CC.
3. Dropped CSRET CC. We cannot add struct return variant for each
target-specific CC (e.g. stdcall + csretcc and so on).
4. Instead of CSRET CC introduced 'sret' parameter attribute. Setting in
on first attribute has meaning 'This is hidden pointer to structure
return. Handle it gently'.
5. Fixed small bug in llvm-extract + add new feature to
FunctionExtraction pass, which relinks all internal-linkaged callees
from deleted function to external linkage. This will allow further
linking everything together.
NOTEs: 1. Documentation will be updated soon.
2. llvm-upgrade should be improved to translate csret => sret.
Before this, there will be some unexpected test fails.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33597 91177308-0d34-0410-b5e6-96231b3b80d8
2007-01-28 13:31:35 +00:00
1ee2925742
Make LABEL a builtin opcode.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33537 91177308-0d34-0410-b5e6-96231b3b80d8
2007-01-26 14:34:52 +00:00
d08d23315d
setSetCCIsExpensive is gone.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32941 91177308-0d34-0410-b5e6-96231b3b80d8
2007-01-05 23:42:53 +00:00
ca367b4e25
Provide support for FP_TO_UINT.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32599 91177308-0d34-0410-b5e6-96231b3b80d8
2006-12-15 14:32:57 +00:00
57fc62c8d2
Another step forward in PPC64 JIT support: we now no-longer need stubs
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emitted for external globals in PPC64-JIT-PIC mode (which is good because
we didn't handle them before!).
This also fixes a bug handling the picbase delta, which we would get wrong
in some cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32451 91177308-0d34-0410-b5e6-96231b3b80d8
2006-12-11 23:22:45 +00:00
2060a822fe
Missing opcode.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32439 91177308-0d34-0410-b5e6-96231b3b80d8
2006-12-11 18:45:56 +00:00
d27a258d2d
Cleaned setjmp/longjmp lowering interfaces. Now we're producing right
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code (both asm & cbe) for Mingw32 target.
Removed autoconf checks for underscored versions of setjmp/longjmp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32415 91177308-0d34-0410-b5e6-96231b3b80d8
2006-12-10 23:12:42 +00:00
85c671b908
Fix i64 uint_to_fp on ppc64
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32297 91177308-0d34-0410-b5e6-96231b3b80d8
2006-12-07 01:24:16 +00:00
efc7e52183
Restoration of the stack pointer after a deallocation of a alloca was not
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updating the SP link.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32202 91177308-0d34-0410-b5e6-96231b3b80d8
2006-12-04 22:04:42 +00:00
fbb74e6941
1. In ppc64 mode we need only use one GPR.
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2. Float values need to be promoted to double when they are vararg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32074 91177308-0d34-0410-b5e6-96231b3b80d8
2006-12-01 16:30:47 +00:00
70fa493613
Fix the CodeGen/PowerPC/vec_constants.ll regression.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32057 91177308-0d34-0410-b5e6-96231b3b80d8
2006-12-01 01:45:39 +00:00
15eb329dae
Fix bug codegen'ing FP constant vectors with integer splats. Make sure the
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created intrinsics have the right integer types. This fixes
PowerPC/2006-11-29-AltivecFPSplat.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32024 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-29 19:58:49 +00:00
619965d32e
Offset for load of 32-bit arg in 64-bit world was incorrect.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32019 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-29 13:37:09 +00:00
7fc4a94bdd
Remove debug code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31970 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-28 18:27:02 +00:00
e9bd7b2e03
32-bit int space was not accounted for properly in lowerCall.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31966 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-28 14:53:52 +00:00
c0f64ffab9
Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead
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of opcode and number of operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31947 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-27 23:37:22 +00:00
b1eb987ccd
on ppc64, float arguments take 8-byte stack slots not 4-byte stack slots.
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Also, valist should create a pointer RC reg class value, not a GPRC value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31840 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-18 01:57:19 +00:00