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4586 Commits

Author SHA1 Message Date
Cameron Zwarich
462b6dc6bf Reuse the TargetInstrDesc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131625 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-19 02:56:23 +00:00
Cameron Zwarich
21803721d5 Correctly constrain a register class when computing frame offsets, as the Thumb2 
add instruction takes an rGPR. This fixes the last of PR8825.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131619 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-19 02:18:27 +00:00
Tanya Lattner
db28247522 Handle perfect shuffle case that generates a vrev for vectors of floats. 
Add test case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131582 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-18 21:44:54 +00:00
Cameron Zwarich
955db42568 Fix more of PR8825. Now all of CodeGen/ARM passes with VerifyCoalescing turned on. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131578 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-18 21:25:14 +00:00
Johnny Chen
a96581f4f7 Disassembly of tBcc was wrongly adding 4 to the SignExtend'ed imm8:'0' immediate operand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131565 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-18 20:32:41 +00:00
Evan Cheng
b936e3006f Revise r131553. Just use the type of the input node and forgo the bitcast. rdar://9449159. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131555 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-18 18:59:17 +00:00
Evan Cheng
d48fda46f5 Fix an ARMTargetLowering::LowerSELECT bug: legalized result must have same type as input. Sorry test cases only trigger when dag combine is disabled. rdar://9449178 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131553 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-18 18:47:27 +00:00
Tanya Lattner
2a8eb722c7 In r131488 I misunderstood how VREV works. It splits the vector in half and splits each half. Therefore, the real problem was that we were using a VREV64 for a 4xi16, when we should have been using a VREV32. 
Updated test case and reverted change to the PerfectShuffle Table.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131529 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-18 06:42:21 +00:00
Cameron Zwarich
141ec63962 Fix typo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131519 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-18 02:29:50 +00:00
Cameron Zwarich
7d336c0c68 Fix more of PR8825 by correctly using rGPR registers when lowering atomic 
compare-and-swap intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131518 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-18 02:20:07 +00:00
Cameron Zwarich
d6ffcd88ba Actually, the address operand of the Thumb2 LDREX / STREX instructions *can* 
take r13, so we can just make it a GPR. This fixes PR8825.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131507 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-17 23:26:20 +00:00
Cameron Zwarich
3c60ff4f3d Correct a minor problem with the Thumb2 LDREX and STREX instruction encodings. They 
were marked as taking a tGPR when in reality they take an rGPR.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131506 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-17 23:11:12 +00:00
Tanya Lattner
c81c9709ef vrev is incorrectly defined in the perfect shuffle table. The ordering is backwards (should be 0x3210 versus 0x1032) which exposed a bug when doing a shuffle on a 4xi16. I've attached a test case. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131488 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-17 20:48:40 +00:00
Jim Grosbach
0c72076190 Kill some dead code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131431 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-16 22:24:07 +00:00
Rafael Espindola
6469540adf sets bit 0 of the function address of thumb function in .symtab 
("T is 1 if the target symbol S has type STT_FUNC and the
symbol addresses a Thumb instruction ;it is 0 otherwise."
from "ELF for the ARM Architecture" 4.7.1.2)

Patch by Koan-Sin Tan!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131406 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-16 16:17:21 +00:00
Owen Anderson
18901d63bf Fix encoding of Thumb BLX register instructions. Patch by Koan-Sin Tan. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131189 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-11 17:00:48 +00:00
Bill Wendling
61512ba251 Give the 'eh.sjlj.dispatchsetup' intrinsic call the value coming from the setjmp 
intrinsic call. This prevents it from being reordered so that it appears
*before* the setjmp intrinsic (thus making it completely useless).
<rdar://problem/9409683>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131174 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-11 01:11:55 +00:00
Jason W Kim
f4351ceb93 First cut at getting debugging support for ARM/MC/ELF/.o 
DWARF stuff also gets fixed up by ELFARMAsmBackend::ApplyFixup(),
but the offset is not guaranteed to be mod 4 == 0 as in text/data. 




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131137 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-10 18:07:25 +00:00
Mon P Wang
183c627d89 Fixed MC encoding for index_align for VLD1/VST1 (single element from one lane) for size 32 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131085 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-09 17:47:27 +00:00
Jakob Stoklund Olesen
ca66226e7e Eliminate the ARM sub-register indexes that are not needed by the sources. 
Tablegen will invent its own names for these indexes, and the register file is a
bit simpler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131059 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-07 21:22:42 +00:00
Eric Christopher
33c110e602 Fix the non-MC encoding of pkhbt and pkhtb. 
Patch by Stephen Hines.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131045 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-07 04:37:27 +00:00
Eli Friedman
fc5d305597 Make the logic for determining function alignment more explicit. No functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131012 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-06 20:34:06 +00:00
Rafael Espindola
f2b0423200 Dead code elimination. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130984 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-06 14:56:22 +00:00
Devang Patel
64915dec28 Do not emit location expression size twice. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130854 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-04 19:00:57 +00:00
Jakob Stoklund Olesen
2944b4fe05 Mark ultra-super-registers QQQQ as call-clobbered instead of the D sub-registers. 
LiveVariables doesn't understand that clobbering D0 and D1 completely overwrites
Q0, so if Q0 is live-in to a function, its live range will extend beyond a
function call that only clobbers D0 and D1. This shows up in the
ARM/2009-11-01-NeonMoves test case.

LiveVariables should probably implement the much stricter rules for physreg
liveness that RAFast imposes - a physreg is killed by the first use of any
alias.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130801 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-03 22:31:24 +00:00
Bob Wilson
e1a56ae747 Temporarily disable use of divmod compiler-rt functions for iOS. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130766 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-03 17:33:22 +00:00
Bruno Cardoso Lopes
0a69ba309f Fold ARM coprocessor intrinsics patterns into the instructions defs whenever 
it's possible.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130764 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-03 17:29:29 +00:00
Bruno Cardoso Lopes
54ad87ab78 Add a few ARM coprocessor intrinsics. Testcases included 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130763 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-03 17:29:22 +00:00
Dan Gohman
cca82149ad Add an unfolded offset field to LSR's Formula record. This is used to 
model constants which can be added to base registers via add-immediate
instructions which don't require an additional register to materialize
the immediate.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130743 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-03 00:46:49 +00:00
Eric Christopher
52f6c03a45 Apparently the check for direct calls is unnecessary. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130716 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-02 20:16:33 +00:00
Eric Christopher
5ac179ccd2 80-col. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130558 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-29 23:12:01 +00:00
Eli Friedman
b451770b26 Zap a couple now-unused functions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130557 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-29 22:56:48 +00:00
Eli Friedman
c573e2c7ea Switch to ImmLeaf (which can be used by FastISel) for a few more common ARM/Thumb2 patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130552 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-29 22:48:03 +00:00
Eric Christopher
d94bc549fc Add FastEmitInst_ii for the arm fast isel generator. It doesn't use it, but 
if it ever did it needs the def machinery.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130549 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-29 22:07:50 +00:00
Eric Christopher
632ae892e6 Some cleanup and optimize fallthrough more. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130546 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-29 21:56:31 +00:00
Eli Friedman
9ebf57ae13 Re-committing r130454, which does not in fact break anything. 
Fix a rather obscure crash caused by ARM fast-isel generating code which redefines a register.
rdar://problem/9338332 .



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130539 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-29 21:22:56 +00:00
Eric Christopher
bcf26aee86 Add trunc->branch support, this won't help with clang's i8->i1 truncations 
for bools, but is a start.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130534 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-29 20:02:39 +00:00
Daniel Dunbar
0eab5c4d85 MCExpr: Add FindAssociatedSection, which attempts to mirror the 'as' semantics 
that associate sections with expressions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130517 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-29 18:00:03 +00:00
Andrew Trick
d49ffe8284 Teach Thumb2 isel to fold and->rotr ==> ROR. 
Generalization of Nate Begeman's patch!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130502 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-29 14:18:15 +00:00
Chris Lattner
d7d030a447 use the MachineInstrBuilder operator-> to simplify some code. 
There are probably more instances of this floating around.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130474 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-29 05:24:29 +00:00
Eric Christopher
6344a5f146 Update comments and checks to match reality. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130464 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-29 00:07:20 +00:00
Eric Christopher
299bbb23a4 Whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130463 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-29 00:03:10 +00:00
Eli Friedman
6e6014cfb3 Revert r130454; apparently this doesn't actually work. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130462 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-28 23:55:14 +00:00
Eli Friedman
2f7fcd7198 Fix a rather obscure crash caused by ARM fast-isel generating code which redefines a register. 
rdar://problem/9338332 .



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130454 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-28 23:03:25 +00:00
Eric Christopher
7a20a37bac Be more layout aware here and swap the successor and branch condition 
if it means we get a fallthrough.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130404 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-28 16:52:09 +00:00
Eric Christopher
8f232d307a Let the immediate leaf pattern take transforms and switch the signed 
immediate patterns in arm to using the pattern.

Handles rdar://9299434


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130386 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-28 05:49:04 +00:00
Devang Patel
c26f5447e3 Teach dwarf writer to handle complex address expression for .debug_loc entries. 
This fixes clang generated blocks' variables' debug info.
Radar 9279956.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130373 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-28 02:22:40 +00:00
Kevin Enderby
e23aea28f9 Fix a bug in the case that there is no add or subtract symbol and the offset 
value is zero so it does not add a NULL expr operand.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130330 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-27 21:02:27 +00:00
Devang Patel
0be77dff11 Revert r130178. It turned out to be not the optimal path to emit complex location expressions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130326 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-27 20:29:27 +00:00
Jim Grosbach
f7da8821b4 ARM and Thumb2 support for atomic MIN/MAX/UMIN/UMAX loads. 
rdar://9326019


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130234 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-26 19:44:18 +00:00