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Author SHA1 Message Date
Nadav Rotem
d6fb53adb1 On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized 
register. In most cases we actually compare or select YMM-sized registers
and mixing the two types creates horrible code. This commit optimizes
some of the transition sequences.

PR14657.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171148 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-27 08:15:45 +00:00
Nadav Rotem
3c22a44400 AVX/AVX2: Move the code that lowers vector-trunc from a DAGCo-hook to custom lowering hook. 
The vector truncs were scalarized during LegalizeVectorOps, later vectorized again by some DAGCombine optimization
and finally, lowered by a dagcombing optimization. Now, they are properly lowered during LegalizeVectorOps.
No new testcase because the original testcases still work.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171146 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-27 07:45:10 +00:00
Craig Topper
068aec586d Add hasSideEffects=0 to some forms of ROUND, RCP, and RSQRT. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171143 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-27 07:16:08 +00:00
Craig Topper
d0f28c0958 Move single letter 'P' prefix out of multiclass now that tablegen allows defm to start with #NAME. This makes instruction names more searchable again. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171141 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-27 06:34:54 +00:00
Craig Topper
87073aad8f Add hasSideEffects=0 to some shift and rotate instructions. None of which are currently used by code generation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171137 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-27 03:35:44 +00:00
Craig Topper
766cbae4b1 Mark the divide instructions as hasSideEffects=0. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171136 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-27 03:01:18 +00:00
Craig Topper
0b9c5e268f Add hasSideEffects=0 to CMP*rr_REV. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171130 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-27 02:08:46 +00:00
Craig Topper
5e6a86c7f0 Add mayLoad, mayStore, and hasSideEffects tags to BT/BTS/BTR/BTC instructions. Shouldn't change any functionality since they don't have patterns to select them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171128 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-27 02:01:33 +00:00
Craig Topper
e9fd6ad567 Fix operands and encoding form for ARPL instruction. Register form had and reversed. Memory form writes memory, but was marked as MRMSrcMem. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171123 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 23:27:57 +00:00
Craig Topper
ee5b63cb52 Add hasSideEffects=0 to some atomic instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171122 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 23:08:12 +00:00
Craig Topper
b87a5b3a1f Mark the AL/AX/EAX forms of the basic arithmetic operations has never having side effects. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171121 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 22:19:23 +00:00
Craig Topper
37cb8398c8 Mark all the _REV instructions as not having side effects. They aren't really emitted by the backend, but it reduces the number of instructions in the output files with unmodelled side effects to make auditing easier. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171118 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 21:30:22 +00:00
Craig Topper
a85cbfeba7 Remove a special conditional setting of neverHasSideEffects if the instruction didn't have a pattern. This was leftover from when tablegen used to complain if things were already inferred from patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171117 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 21:04:30 +00:00
Craig Topper
0a5ead92ff Merge still more SSE/AVX instruction definitions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171103 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 07:54:43 +00:00
Craig Topper
07555fc640 Merge more SSE/AVX instruction definitions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171102 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 07:20:35 +00:00
Craig Topper
755841d9d7 Fix 80 column violation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171097 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 06:15:53 +00:00
Craig Topper
6f9d44e072 Fix class name in comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171096 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 06:15:09 +00:00
Craig Topper
219bc2db1f Merge SSE/AVX PCMPEQ/PCMPGT instruction definitions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171095 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 06:14:15 +00:00
Craig Topper
02082efaab Remove 'v' from mnemonic to fix asm matching failures. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171093 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 06:02:15 +00:00
Craig Topper
3cdc3827ce Use an additional multiclass to merge the 128/256-bit SSE/AVX instruction definitions for a bunch of SSE2 integer arithmetic instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171092 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 05:49:15 +00:00
Nadav Rotem
a05f7cbbde Reformat the docs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171091 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 04:59:20 +00:00
Craig Topper
09a326d3f0 Use an additional multiclass to merge the 128/256-bit SSE/AVX instruction definitions for PAND/POR/PXOR/PANDN 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171087 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 04:36:03 +00:00
Craig Topper
1fe132ae7d Merge an AVX/SSE 256-bit and 128-bit multiclass. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171086 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 03:56:47 +00:00
Craig Topper
b5c590a586 Mark VANDNPD/VANDNPDS as not commutable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171085 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 03:48:10 +00:00
Craig Topper
174a3d3e63 Remove alignment from a bunch more VEX encoded operations in the folding tables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171082 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 02:44:47 +00:00
Craig Topper
d83a73adf0 Remove alignment from folding table for VMOVUPD as an unaligned instruction it shouldn't require alignment... 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171081 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 02:14:19 +00:00
Craig Topper
1ac0046fa8 Remove alignment requirements from (V)EXTRACTPS. This instruction does 32-bit stores which aren't required to be aligned on SSE or AVX. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171080 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 01:47:12 +00:00
Craig Topper
0f77910e6f Remove alignment requirement from VCVTSS2SD in folding tables. Reverting r171049. This instruction doesn't require alignment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171078 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 00:35:47 +00:00
Hal Finkel
cd9ea51986 Expand PPC64 atomic load and store 
Use of store or load with the atomic specifier on 64-bit types would
cause instruction-selection failures. As with the 32-bit case, these
can use the default expansion in terms of cmp-and-swap.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171072 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-25 17:22:53 +00:00
Benjamin Kramer
99f78061e0 X86: Shave off one shuffle from the pcmpeqq sequence for SSE2 by making use of and commutativity. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171064 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-25 13:09:08 +00:00
Benjamin Kramer
382ed78d3f X86: Custom lower <2 x i64> eq and ne when SSE41 is not available. 
pcmpeqd, pshufd, pshufd, pand is cheaper than unpack + cmpq, sbbq, cmpq, sbbq + pack.
Small speedup on loop-vectorized viterbi (-march=core2).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171063 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-25 12:54:19 +00:00
Nadav Rotem
a4c8a32a9f VCVTSS2SD requires a strict alignment. Thanks Elena. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171049 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-25 03:29:18 +00:00
Nick Lewycky
71f30bffcf Quiet gcc's -Wparenthesis warning. No functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171044 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-24 19:58:45 +00:00
Benjamin Kramer
791dbb3e5f Use a std::string rather than a dynamically allocated char* buffer. 
This affords us to use std::string's allocation routines and use the destructor
for the memory management. Switching to that also means that we can use
operator==(const std::string&, const char *) to perform the string comparison
rather than resorting to libc functionality (i.e. strcmp).

Patch by Saleem Abdulrasool!

Differential Revision: http://llvm-reviews.chandlerc.com/D230

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171042 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-24 19:23:30 +00:00
Nadav Rotem
1e1c5f37c3 CostModel: We have API for checking the costs of known shuffles. This patch adds 
support for the insert-subvector and extract-subvector kinds.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171027 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-24 10:04:03 +00:00
Nadav Rotem
ace0c2fad7 Some x86 instructions can load/store one of the operands to memory. On SSE, this memory needs to be aligned. 
When these instructions are encoded in VEX (on AVX) there is no such requirement. This changes the folding
tables and removes the alignment restrictions from VEX-encoded instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171024 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-24 09:40:33 +00:00
Nadav Rotem
daf7b5c8f2 Change the codegen Cost Model API for shuffeles. This patch removes the API for broadcast and adds a more general API that accepts an enum of known shuffles. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171022 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-24 08:57:47 +00:00
Nadav Rotem
6f3d81a929 CostModel: Change the default target-independent implementation for finding 
the cost of arithmetic functions. We now assume that the cost of arithmetic
operations that are marked as Legal or Promote is low, but ops that are
marked as custom are higher.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171002 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-23 17:31:23 +00:00
Nadav Rotem
40b04a481d whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170997 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-23 07:33:44 +00:00
Nadav Rotem
677689cf5d Rename a function. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170996 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-23 07:30:09 +00:00
Nadav Rotem
d54fed2786 Loop Vectorizer: Update the cost model of scatter/gather operations and make 
them more expensive.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170995 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-23 07:23:55 +00:00
Benjamin Kramer
2f8a6cdfa3 X86: Turn mul of <4 x i32> into pmuludq when no SSE4.1 is available. 
pmuludq is slow, but it turns out that all the unpacking and packing of the
scalarized mul is even slower. 10% speedup on loop-vectorized paq8p.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170985 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-22 16:07:56 +00:00
Benjamin Kramer
17347912b4 X86: Emit vector sext as shuffle + sra if vpmovsx is not available. 
Also loosen the SSSE3 dependency a bit, expanded pshufb + psra is still better
than scalarized loads. Fixes PR14590.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170984 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-22 11:34:28 +00:00
Nadav Rotem
d0696ef8c3 In some cases, due to scheduling constraints we copy the EFLAGS. 
The only way to read the eflags is using push and pop. If we don't
adjust the stack then we run over the first frame index. This is
not something that we want to do, so we have to make sure that
our machine function does not copy the flags. If it does then
we have to emit the prolog that adjusts the stack.

rdar://12896831



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170961 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-21 23:48:49 +00:00
Akira Hatanaka
dbf51ee459 [mips] Refactor subword-swap, EXT/INS, load-effective-address and read-hardware 
instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170956 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-21 23:21:32 +00:00
Akira Hatanaka
e8bc10b902 [mips] Refactor SYNC and multiply/divide instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170955 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-21 23:17:36 +00:00
Akira Hatanaka
aa7c9cd181 [mips] Refactor BAL instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170954 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-21 23:15:59 +00:00
Akira Hatanaka
1892253694 [mips] Fix encoding of BAL instruction. Also, fix assembler test case which 
was not catching the error.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170953 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-21 23:13:59 +00:00
Akira Hatanaka
6a8309e62a [mips] Refactor jump, jump register, jump-and-link and nop instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170952 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-21 23:03:50 +00:00
Akira Hatanaka
0a57dc1d14 [mips] Refactor load/store left/right and load-link and store-conditional 
instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170950 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-21 23:01:24 +00:00