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Author SHA1 Message Date
Elena Demikhovsky
1596373671 Shuffle optimization for AVX/AVX2. 
The current patch optimizes frequently used shuffle patterns and gives these instruction sequence reduction.
Before:
      vshufps $-35, %xmm1, %xmm0, %xmm2 ## xmm2 = xmm0[1,3],xmm1[1,3]
       vpermilps       $-40, %xmm2, %xmm2 ## xmm2 = xmm2[0,2,1,3]
       vextractf128    $1, %ymm1, %xmm1
       vextractf128    $1, %ymm0, %xmm0
       vshufps $-35, %xmm1, %xmm0, %xmm0 ## xmm0 = xmm0[1,3],xmm1[1,3]
       vpermilps       $-40, %xmm0, %xmm0 ## xmm0 = xmm0[0,2,1,3]
       vinsertf128     $1, %xmm0, %ymm2, %ymm0
After:
      vshufps $13, %ymm0, %ymm1, %ymm1 ## ymm1 = ymm1[1,3],ymm0[0,0],ymm1[5,7],ymm0[4,4]
      vshufps $13, %ymm0, %ymm0, %ymm0 ## ymm0 = ymm0[1,3,0,0,5,7,4,4]
      vunpcklps       %ymm1, %ymm0, %ymm0 ## ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159188 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-26 08:04:10 +00:00
Craig Topper
952caee4f6 Remove some duplicate instructions that exist only to given different mnemonics for the assembler. Use InstAlias instead. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159184 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-26 04:12:49 +00:00
Eli Friedman
52d418df5d Make some ugly hacks for inline asm operands which name a specific register a bit more thorough. PR13196. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159176 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-25 23:42:33 +00:00
Craig Topper
fd1753bedb Add SSE2 predicate to CVTPS2PD instructions. Doesn't matter much because there are no patterns in the instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159127 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-25 06:51:42 +00:00
Craig Topper
13d89c7976 Remove codegen only instruction in favor of one that has the same definition. Make some pattern operands more explicit about types. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159126 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-25 06:16:00 +00:00
Jakob Stoklund Olesen
82d58b147f %RCX is not a function live-out in eh.return functions. 
The function live-out registers must be live at all function returns,
and %RCX is only used by eh.return. When a function also has a normal
return, only %RAX holds a return value.

This fixes PR13188.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159116 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-24 15:53:01 +00:00
NAKAMURA Takumi
d5c407d2d0 llvm/lib: [CMake] Add explicit dependency to intrinsics_gen. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159112 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-24 13:32:01 +00:00
Craig Topper
e7f702fc2d Remove intrinsic specific instructions for (V)CVTPS2DQ and replace with patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159109 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-24 07:07:16 +00:00
Craig Topper
2123b18247 Remove intrinsic specific instructions for (V)CVTPS2DQ and replace with patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159108 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-24 06:55:37 +00:00
Craig Topper
081f931077 Fix build failures from r159106. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159107 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-24 06:08:31 +00:00
Craig Topper
66a69fa729 Remove intrinsic specific instructions for CVTPD2PS and replace with just patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159106 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-24 05:44:31 +00:00
Craig Topper
7f2ea14c68 Remove intrinsic specific instructions for CVTPD2DQ. Replace with patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159105 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-24 05:33:24 +00:00
Pete Cooper
6e2db65266 Remove code i'd been testing with but didn't mean to commit. Oops 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159094 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-24 00:08:36 +00:00
Pete Cooper
b49998d76c DAG legalisation can now handle illegal fma vector types by scalarisation 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159092 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-24 00:05:44 +00:00
Craig Topper
c82b9a51a2 Remove intrinsic specific instructions for (V)CVTDQ2PS. Use a Pat instead instead. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159090 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-23 22:33:14 +00:00
Craig Topper
624a9c49d4 Make CVTDQ2PS instruction use SSE2 predicate instead of SSE1. No functional change because there are no patterns in the instructions. Also fix a typo in a comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159087 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-23 20:52:45 +00:00
Craig Topper
6fc218e3a1 Move CVTPD2DQ to use SSE2 predicate instead of SSE3. Move DQ2PD and PD2DQ to the SSE2 section of the file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159086 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-23 20:15:42 +00:00
Craig Topper
fc76b8691e Use correct memory types for (V)CVTDQ2PD instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159075 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-23 08:30:27 +00:00
Craig Topper
3ed920f308 Compress flags in X86 op folding to reduce space in static tables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159073 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-23 08:01:18 +00:00
Craig Topper
f318457547 Make helper method static since it doesn't use anything in the class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159071 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-23 04:58:41 +00:00
Craig Topper
eea4a9b1e6 Remove intrinsic specific instructions for 128-bit (V)CVTDQ2PD. Replace with intrinsic patterns. Mem forms omitted because the load size is only 64-bits. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159070 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-23 04:23:36 +00:00
Rafael Espindola
ce0a5cda8a Handle aliases to tls variables in all architectures, not just x86. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159058 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-23 00:30:03 +00:00
Chad Rosier
670712ca3f Whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159035 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-22 22:07:19 +00:00
Jakob Stoklund Olesen
e208c49172 Functions calling __builtin_eh_return must have a frame pointer. 
The code in X86TargetLowering::LowerEH_RETURN() assumes that a frame
pointer exists, but the frame pointer was forced by the presence of
llvm.eh.unwind.init which isn't guaranteed.

If llvm.eh.unwind.init is actually required in functions calling
eh.return (is it?), we should diagnose that instead of emitting bad
machine code.

This should fix the dragonegg-x86_64-linux-gcc-4.6-test bot.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158961 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-22 03:04:27 +00:00
Chandler Carruth
305b515c27 Remove 'static' from inline functions defined in header files. 
There is a pretty staggering amount of this in LLVM's header files, this
is not all of the instances I'm afraid. These include all of the
functions that (in my build) are used by a non-static inline (or
external) function. Specifically, these issues were caught by the new
'-Winternal-linkage-in-inline' warning.

I'll try to just clean up the remainder of the clearly redundant "static
inline" cases on functions (not methods!) defined within headers if
I can do so in a reliable way.

There were even several cases of a missing 'inline' altogether, or my
personal favorite "static bool inline". Go figure. ;]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158800 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-20 08:39:33 +00:00
Craig Topper
65d36f0367 Add predicate check around some patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158797 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-20 07:30:23 +00:00
Craig Topper
af4166cd09 Add predicate check around some patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158795 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-20 07:01:11 +00:00
Craig Topper
703c38bf58 Don't insert 128-bit UNDEF into 256-bit vectors. Just keep the 256-bit vector. Original patch by Elena Demikhovsky. Tweaked by me to allow possibility of covering more cases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158792 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-20 05:39:26 +00:00
Rafael Espindola
d6b43a317e Move the support for using .init_array from ARM to the generic 
TargetLoweringObjectFileELF. Use this to support it on X86. Unlike ARM,
on X86 it is not easy to find out if .init_array should be used or not, so
the decision is made via TargetOptions and defaults to off.

Add a command line option to llc that enables it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158692 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-19 00:48:28 +00:00
Chandler Carruth
43369249e7 Temporarily revert r158087. 
This patch causes problems when both dynamic stack realignment and
dynamic allocas combine in the same function. With this patch, we no
longer build the epilog correctly, and silently restore registers from
the wrong position in the stack.

Thanks to Matt for tracking this down, and getting at least an initial
test case to Chad. I'm going to try to check a variation of that test
case in so we can easily track the fixes required.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158654 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-18 07:03:12 +00:00
Kay Tiong Khoo
19e5015e5f *no need to pollute Intel syntax with bonus mnemonics; operand size is explicitly specified 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158603 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-16 17:19:49 +00:00
Kay Tiong Khoo
695fd1a455 *fixed to separate mnemonic from operands with tab 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158543 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-15 21:04:21 +00:00
Craig Topper
8e58b3e9b8 Move AVX version of convert instructions that write to GPRs to the Op1 table. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158497 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-15 07:02:58 +00:00
Pete Cooper
312091ece3 Move X86::VCVTTSD2SIrr from the 2 operand to 1 operand MemRegOp table. 
Can someone with more knowledge of this please look at other entries
to see if others need moved.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158474 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-14 22:12:58 +00:00
Craig Topper
cc95b57d42 Fix intrinsics for XOP frczss/sd instructions. These instructions only take one source register and zero the upper bits of the destination rather than preserving them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158396 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-13 07:18:53 +00:00
Craig Topper
cfd3ed9eaf Add intrinsics for immediate form of XOP vprot instructions. Use i128mem instead of f128mem for integer XOP instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158291 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-10 07:31:56 +00:00
Craig Topper
2a5dc43bd9 Use XOP vpcom intrinsics in patterns instead of a target specific SDNode type. Remove the custom lowering code that selected the SDNode type. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158279 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-09 17:02:24 +00:00
Craig Topper
c29106b36f Replace XOP vpcom intrinsics with fewer intrinsics that take the immediate as an argument. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158278 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-09 16:46:13 +00:00
Manman Ren
45d53b866e Enable optimization for integer ABS on X86 if Subtarget has CMOV. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158220 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-08 18:58:26 +00:00
Manman Ren
9236362a64 X86: optimize generated code for integer ABS 
This patch will generate the following for integer ABS:
      movl    %edi, %eax
      negl    %eax
      cmovll  %edi, %eax
INSTEAD OF
      movl    %edi, %ecx
      sarl    $31, %ecx
      leal    (%rdi,%rcx), %eax
      xorl    %ecx, %eax

There exists a target-independent DAG combine for integer ABS, which converts
integer ABS to sar+add+xor. For X86, we match this pattern back to neg+cmov. 
This is implemented in PerformXorCombine.

rdar://10695237


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158175 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-07 22:39:10 +00:00
Nadav Rotem
bdcae38256 Do not optimize the used bits of the x86 vselect condition operand, when the condition operand is a vector of 1-bit predicates. 
This may happen on MIC devices.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158168 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-07 20:53:48 +00:00
Manman Ren
e6fc9d40b3 PR13046: we can't replace usage of SUB with CMP in the lowering phase. 
It will cause assertion failure later on.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158160 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-07 19:27:33 +00:00
Rafael Espindola
c07f5bbd3b Use a base register instead of an index register with the local dynamic model. 
Fixes pr13048.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158158 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-07 18:39:19 +00:00
Manman Ren
87253c2ebd X86: replace SUB with CMP if possible 
This patch will optimize the following
    movq    %rdi, %rax
    subq    %rsi, %rax
    cmovsq  %rsi, %rdi
    movq    %rdi, %rax
to
    cmpq    %rsi, %rdi
    cmovsq  %rsi, %rdi
    movq    %rdi, %rax

Perform this optimization if the actual result of SUB is not used.

rdar: 11540023


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158126 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-07 00:42:47 +00:00
Manman Ren
2afde7782d Revert r157755. 
The commit is intended to fix rdar://11540023.
It is implemented as part of peephole optimization. We can actually implement
this in the SelectionDAG lowering phase.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158122 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-06 23:53:03 +00:00
Benjamin Kramer
a7542d5f87 Remove unused private fields found by clang's new -Wunused-private-field. 
There are some that I didn't remove this round because they looked like
obvious stubs. There are dead variables in gtest too, they should be
fixed upstream.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158090 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-06 18:25:08 +00:00
Chad Rosier
a97b180fc4 Add support for dynamic stack realignment in the presence of dynamic allocas on 
X86.
rdar://11496434


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158087 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-06 17:37:40 +00:00
Craig Topper
3949b8382d Mark several instructions SSE2 instead of SSE3 as they should be. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158049 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-06 06:45:27 +00:00
Andrew Trick
1d98530196 X86 itinerary properties. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157981 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-05 03:44:46 +00:00
Andrew Trick
d05b46115f whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157976 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-05 03:44:29 +00:00