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d725189254
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6996 Commits

Author SHA1 Message Date
David Greene
d725189254 Fix DejaGNU run line to escape special characters. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73090 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-08 22:20:58 +00:00
David Greene
e1b469170b Make IntInits and ListInits typed. This helps deduce types of !if and 
other operators.  For the rare cases where a list type cannot be
deduced, provide a []<type> syntax, where <type> is the list element
type.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73078 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-08 20:23:18 +00:00
David Greene
938c8ab0a0 Add a !regmatch operator to do pattern matching in TableGen. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73074 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-08 17:00:34 +00:00
Eli Friedman
faeedf1254 Fix the run-line for this test to work correctly outside of x86. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73025 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-07 09:44:19 +00:00
Eli Friedman
f10d3a7bcd Tweak the expansion code for BIT_CONVERT to generate better code 
converting from an MMX vector to an i64.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73024 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-07 09:41:57 +00:00
Eli Friedman
7a5e55509b Slightly generalize the code that handles shuffles of consecutive loads 
on x86 to handle more cases.  Fix a bug in said code that would cause it 
to read past the end of an object.  Rewrite the code in 
SelectionDAGLegalize::ExpandBUILD_VECTOR to be a bit more general. 
Remove PerformBuildVectorCombine, which is no longer necessary with 
these changes.  In addition to simplifying the code, with this change, 
we can now catch a few more cases of consecutive loads.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73012 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-07 06:52:44 +00:00
Eli Friedman
0da9975299 PR3628: Add patterns to match SHL/SRL/SRA to the corresponding Altivec 
instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73009 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-07 01:07:55 +00:00
Eli Friedman
b9a4cacc91 PR4340: Run SimplifyDemandedVectorElts on insertelement instructions; 
sometimes it can find simplifications that won't be found otherwise.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73006 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-06 20:08:03 +00:00
Eli Friedman
5257106c4d Fix the expansion for CONCAT_VECTORS so that it doesn't create illegal 
types.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72993 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-06 07:08:26 +00:00
Eli Friedman
30e71eb61b Avoid crashing on a variable-index insertelement with element type i16. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72991 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-06 06:32:50 +00:00
Eli Friedman
1041553424 Get rid of some bogus patterns for X86vzmovl. Don't create VZEXT_MOVL 
nodes for vectors with an i16 element type.  Add an optimization for 
building a vector which is all zeros/undef except for the bottom 
element, where the bottom element is an i8 or i16.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72988 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-06 06:05:10 +00:00
Eli Friedman
9d47b8d8ea Fix an obvious typo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72987 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-06 05:55:37 +00:00
Eli Friedman
1762c1439e Get rid of a bogus pattern that interferes with optimization. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72985 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-06 04:17:04 +00:00
Eli Friedman
23ef105580 PR2598: make sure to expand illegal forms of integer/floating-point 
conversions for x86, like <2 x i32> -> <2 x float> and <4 x i16> -> 
<4 x float>.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72983 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-06 03:57:58 +00:00
Devang Patel
578efa920a Add new function attribute - noimplicitfloat 
Update code generator to use this attribute and remove NoImplicitFloat target option.
Update llc to set this attribute when -no-implicit-float command line option is used.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72959 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-05 21:57:13 +00:00
Nate Begeman
abc0199680 Adapt the x86 build_vector dagcombine to the current state of the legalizer. 
build vectors with i64 elements will only appear on 32b x86 before legalize.
Since vector widening occurs during legalize, and produces i64 build_vector 
elements, the dag combiner is never run on these before legalize splits them
into 32b elements.

Teach the build_vector dag combine in x86 back end to recognize consecutive 
loads producing the low part of the vector.

Convert the two uses of TLI's consecutive load recognizer to pass LoadSDNodes
since that was required implicitly.

Add a testcase for the transform.

Old:
	subl	$28, %esp
	movl	32(%esp), %eax
	movl	4(%eax), %ecx
	movl	%ecx, 4(%esp)
	movl	(%eax), %eax
	movl	%eax, (%esp)
	movaps	(%esp), %xmm0
	pmovzxwd	%xmm0, %xmm0
	movl	36(%esp), %eax
	movaps	%xmm0, (%eax)
	addl	$28, %esp
	ret

New:
	movl	4(%esp), %eax
	pmovzxwd	(%eax), %xmm0
	movl	8(%esp), %eax
	movaps	%xmm0, (%eax)
	ret




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72957 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-05 21:37:30 +00:00
Evan Cheng
925492279a Changing allocation ordering from r3 ... r0 back to r0 ... r3. The order change no longer make sense after the coalescing changes we have made since then. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72955 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-05 19:08:58 +00:00
Dan Gohman
9f5f322a03 Fix an erroneous check for isFNeg; the FNeg case is handled 
a few lines later on.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72904 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-04 23:43:29 +00:00
Bill Wendling
40e233f103 Fix these so that they work on non-x86 Darwin machines. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72903 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-04 23:37:19 +00:00
Bill Wendling
46b89af1ae Specify that this works for Darwin. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72899 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-04 22:56:29 +00:00
Dan Gohman
ae3a0be92e Split the Add, Sub, and Mul instruction opcodes into separate 
integer and floating-point opcodes, introducing
FAdd, FSub, and FMul.

For now, the AsmParser, BitcodeReader, and IRBuilder all preserve
backwards compatability, and the Core LLVM APIs preserve backwards
compatibility for IR producers. Most front-ends won't need to change
immediately.

This implements the first step of the plan outlined here:
http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72897 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-04 22:49:04 +00:00
Devang Patel
d18e31ae17 Add new function attribute - noredzone. 
Update code generator to use this attribute and remove DisableRedZone target option.
Update llc to set this attribute when -disable-red-zone command line option is used.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72894 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-04 22:05:33 +00:00
Evan Cheng
073e7e5807 RALinScan::attemptTrivialCoalescing() was returning a virtual register instead of the physical register it is allocated to. This resulted in virtual register(s) being added the live-in sets. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72890 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-04 20:53:36 +00:00
Evan Cheng
cd0c4ac7fb A value defined by an implicit_def can be liven to a use BB. This is unfortunate. But register allocator still has to add it to the live-in set of the use BB. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72888 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-04 20:25:48 +00:00
Dale Johannesen
1e07efd59d For XTARGET to work on targets not in the list, 
there must also be an XFAIL line.  Fix a couple
examples of this.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72876 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-04 18:27:43 +00:00
Dan Gohman
0e19a3f89e Check in test changes that I accidentally left out of r72872. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72875 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-04 18:22:31 +00:00
Eli Friedman
bccf4b3050 PR3739, part 2: Use an explicit store to spill XMM registers. (Previously, 
the code tried to use "push", which doesn't exist for XMM registers.)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72836 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-04 02:32:04 +00:00
Eli Friedman
9a41712122 PR3739, part 1: Disable the red zone on Win64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72830 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-04 02:02:01 +00:00
Evan Cheng
1488326156 Re-apply 72756 with fixes. One of those was introduced by we changed MachineInstrBuilder::addReg() interface. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72826 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-04 01:15:28 +00:00
Eli Friedman
a8ba2c25e9 PR4317: Handle splits where the new block is unreachable correctly in 
DominatorTreeBase::Split.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72810 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-03 21:42:06 +00:00
Evan Cheng
424f8f339a For Darwin / x86_64, override -relocation-model=static to pic if the output is assembly since Darwin assembler does not really support -static codeine. 
I view this as a temporary workaround until the assembler / linker changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72806 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-03 21:13:54 +00:00
Dan Gohman
68c9344056 Don't attempt to simplify an non-affine IV expression if it can't 
be simplified to a loop-invariant value. This fixes PR4315.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72798 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-03 19:11:31 +00:00
Evan Cheng
2c48fe6757 Fix for PR4225: When rewriter reuse a value in a physical register , it clear the register kill operand marker and its kill ops information. However, the cleared operand may be a def of a super-register. Clear the kill ops info for the super-register's sub-registers as well. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72758 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-03 09:00:27 +00:00
Evan Cheng
70fd60bd57 Temporarily revert 72756 for now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72757 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-03 07:40:47 +00:00
Evan Cheng
9d5fb981b0 Fold preceding / trailing base inc / dec into the single load / store as well. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72756 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-03 06:14:58 +00:00
Dan Gohman
6ecc2602a6 Revert r72734. The Darwin assembler doesn't support the static 
relocation model on x86-64. Higher level logic should override
the relocation model to PIC on x86_64-apple-darwin.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72746 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-03 00:37:20 +00:00
Dan Gohman
8b0d4f61bb Fix CodeGenPrepare's address-mode sinking to handle unusual 
addresses, involving Base values which do not have Pointer type.
This fixes PR4297.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72739 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-02 21:29:13 +00:00
Evan Cheng
da9863fa41 On Darwin x86_64 small code model doesn't guarantee code address fits in 32-bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72734 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-02 20:09:31 +00:00
Evan Cheng
5d16396a33 Avoid infinite looping in AllGlobalLoadUsesSimpleEnoughForHeapSRA(). This can happen when PHI uses are recursively dependent on each other. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72710 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-02 00:56:07 +00:00
Eli Friedman
41b33f437f PR4286: Make RewriteLoadUserOfWholeAlloca and 
RewriteStoreUserOfWholeAlloca deal with tail padding because 
isSafeUseOfBitCastedAllocation expects them to.  Otherwise, we crash 
trying to erase the bitcast.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72688 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-01 09:14:32 +00:00
Owen Anderson
88554df4a2 Be more aggressive in doing LoadPRE by tracing backwards when a block only has 
a single predecessor.

Patch by Jakub Staszak.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72661 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-31 09:03:40 +00:00
Chris Lattner
0e98e4d299 fix PR4284, a bug in simplifylibcalls handling memcmp. Patch by 
Benjamin Kramer!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72625 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-30 18:43:04 +00:00
Duncan Sands
46c403d815 Adjust these tests now that "extern inline" 
functions are being output with bodies and
available_externally linkage.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72620 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-30 13:57:05 +00:00
Evan Cheng
cf7895ff8b (i64 (zext (srl GR32 8))) -> movzbl AH is not safe since srl 8 only clear the top 8 bits. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72618 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-30 08:43:27 +00:00
Nick Lewycky
7a0370f66a Give embedded metadata its own type instead of relying on EmptyStructTy. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72610 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-30 05:06:04 +00:00
Duncan Sands
44008257a4 Dan noticed that the verifier wasn't thoroughly checking uses of 
invoke results (see the testcases).  Tighten up the checking.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72586 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-29 19:39:36 +00:00
Evan Cheng
8e610a7784 Remove an accidental commit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72560 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-29 05:28:52 +00:00
Evan Cheng
cb219f0ef6 More h-registers tricks: folding zext nodes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72558 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-29 01:44:43 +00:00
Evan Cheng
d3c76bb6fc Do not try to create a MVT type of width 0. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72557 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-28 23:52:18 +00:00
Eli Friedman
f1f7c09390 Add explicit test for PR4280. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72539 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-28 21:04:35 +00:00