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3293 Commits

Author SHA1 Message Date
Bill Wendling
dd3bc112e6 Add encoding for VSUB and VCMP. 
Fear not! I'm going to try a refactoring right now. :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116359 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 22:55:35 +00:00
Bill Wendling
174777bb2b Encoding for VADDD. Plus a test for the VFP instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116348 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 22:08:41 +00:00
Bill Wendling
a0c14ef8f6 Split out the "size" field from the encoding. The newer documentation has it as 
a separate bit in the coding.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116347 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 22:03:19 +00:00
Eric Christopher
558cf007b5 Fix thinko in arm fast isel alloca rewrite. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116339 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 21:23:43 +00:00
Jim Grosbach
499e886fe6 Encoding for ARM-mode VADD.F32 instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116338 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 21:22:40 +00:00
Jim Grosbach
f59818b81a Add MOVi ARM encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116321 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 18:09:12 +00:00
Jim Grosbach
8e157302f4 Nuke unused wrapper function. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116318 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 17:53:25 +00:00
Jim Grosbach
0de6ab3c43 Add encoding information for the remainder of the generic arithmetic 
ARM instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116313 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 17:11:26 +00:00
Bob Wilson
77f42b5278 PR8359: The ARM backend may end up allocating registers D16 to D31 when 
"-mattr=+vfp3" is specified. However, this will not work for hardware that
only supports 16 registers.  Add a new flag to support -"mattr=+vfp3,+d16".
Patch by Jan Voung!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116310 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 16:22:47 +00:00
Eric Christopher
1541877941 Rework alloca handling so that we can load or store from casted 
address that we've looked through.

Fixes compilation problems in tramp3d from earlier patch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116296 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 05:39:06 +00:00
Eric Christopher
5532433a57 Handle a wider arrangement of loads. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116284 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 00:43:21 +00:00
Evan Cheng
08cec1ef27 More ARM scheduling itinerary fixes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116266 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 23:41:41 +00:00
Jim Grosbach
42fac8ee3b MC machine encoding for simple aritmetic instructions that use a shifted 
register operand.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116259 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 23:16:21 +00:00
Jason W Kim
17b443df43 Second set of ARM/MC/ELF changes. 
Added ARM specific ELF section types.
Added AttributesSection to ARMElfTargetObject
First step in unifying .cpu assembly tag with ELF/.o
llc now asserts on actual ELF emission on -filetype=obj :-)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116257 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 23:01:44 +00:00
Evan Cheng
60ff87914f Proper VST scheduling itineraries. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116251 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 22:03:18 +00:00
Eric Christopher
5f9e8b971b Use a sane mechanism for that assert. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116249 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 22:01:22 +00:00
Eric Christopher
050d16c2a9 We're not going to handle dynamic allocas anywhere else. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116240 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 21:37:35 +00:00
Eric Christopher
fb0b892f7e Make sure that the call stack adjustments have default operands. Also 
leave custom lowerings for later.

Fixes some nightly tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116232 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 21:20:02 +00:00
Eric Christopher
8ff9a9da0a Found a bug turning this on by default. Disable again for now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116220 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 20:26:21 +00:00
Eric Christopher
fa6b29dacd Fix help text. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116218 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 20:15:02 +00:00
Eric Christopher
feadddd6b6 Change flag from Enable to Disable since we're enabled by default. 
Also don't use fast-isel on non-darwin since it's untested.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116217 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 20:05:22 +00:00
Jim Grosbach
62547267f0 More binary encoding stuff, taking advantage of the new "by name" operand 
matching in tblgen to do the predicate operand.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116213 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 18:51:51 +00:00
Eric Christopher
a2efc5ff6e Turn on arm fast isel by default. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116212 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 18:48:18 +00:00
Francois Pichet
1265776243 MSVC hangs on compilation of ARMDisassembler.cpp. PR6866 applied to ARM target. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116201 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 11:36:19 +00:00
Eric Christopher
a1640d9ed9 Copy and pasteo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116198 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 08:40:05 +00:00
Eric Christopher
dccd2c3c43 Whitespace cleanup in ARM fast isel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116197 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 08:38:55 +00:00
Eric Christopher
6a880d6ba8 Add srem libcall support to ARM fast isel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116196 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 08:37:26 +00:00
Eric Christopher
7bdc4de4e7 Add i8 sdiv support for ARM fast isel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116195 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 08:31:54 +00:00
Eric Christopher
3bbd396853 Implement select handling for ARM fast-isel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116194 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 08:27:59 +00:00
Evan Cheng
10dc63feeb Add VLD4 scheduling itineraries. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116143 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-09 04:07:58 +00:00
Evan Cheng
84f69e8436 Finish vld3 and vld4. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116140 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-09 01:45:34 +00:00
Evan Cheng
40bb6836f6 Complete vld2 instruction itineries. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116136 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-09 01:26:12 +00:00
Evan Cheng
8ae6ffacdd Multiply instructions are issued on pipeline 0. They do not need to reserve pipeline 1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116135 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-09 01:15:04 +00:00
Evan Cheng
d2ca813549 Correct some load / store instruction itinerary mistakes: 
1. Cortex-A8 load / store multiplies can only issue on ALU0.
2. Eliminate A8_Issue, A8_LSPipe will correctly limit the load / store issues.
3. Correctly model all vld1 and vld2 variants.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116134 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-09 01:03:04 +00:00
Bill Wendling
0aa38b9381 Check to make sure that the iterator isn't at the beginning of the basic block 
before decrementing. <rdar://problem/8529919>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116126 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-09 00:03:48 +00:00
Eric Christopher
e93417bcc8 Fix the store part of this as well. Fixes smg2000. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116123 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-08 23:52:16 +00:00
Jim Grosbach
56ac907c57 Implement a few more binary encoding bits. Still very early stage proof-of- 
concept level stuff at this point, but it is generally working for those
instructions that know how to map the operands.

This patch fills in the register operands for add/sub/or/etc instructions
and adds the conditional execution predicate encoding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116112 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-08 21:45:55 +00:00
Jim Grosbach
3e09413c2c Reapply 116059, this time without the fatfingered pasto at the top. 
''const'ify getMachineOpValue() and associated helpers.'

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116067 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-08 17:45:54 +00:00
Jim Grosbach
2cee75a254 Reverting 116059. Bots are unhappy with it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116064 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-08 17:28:40 +00:00
Jim Grosbach
461caba214 'const'ify getMachineOpValue() and associated helpers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116059 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-08 16:52:44 +00:00
Bob Wilson
7d24705f65 Change register allocation order for ARM VFP and NEON registers to put the 
callee-saved registers at the end of the lists.  Also prefer to avoid using
the low registers that are in register subclasses required by certain
instructions, so that those registers will more likely be available when needed.
This change makes a huge improvement in spilling in some cases.  Thanks to
Jakob for helping me realize the problem.

Most of this patch is fixing the testsuite.  There are quite a few places
where we're checking for specific registers.  I changed those to wildcards
in places where that doesn't weaken the tests.  The spill-q.ll and
thumb2-spill-q.ll tests stopped spilling with this change, so I added a bunch
of live values to force spills on those tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116055 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-08 06:15:13 +00:00
Eric Christopher
7a56f33583 Move to thumb2 loads, fixes a problem with incoming registers 
as thumb1.

Fixes lencod.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116027 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-08 01:13:17 +00:00
Jim Grosbach
58f38bfa24 Enable binary encoding of some simple instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116022 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-08 00:39:21 +00:00
Jim Grosbach
bade37bb8b Make <target>CodeEmitter::getBinaryCodeForInstr() a const method. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116018 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-08 00:21:28 +00:00
Evan Cheng
344d9db970 Code refactoring. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116002 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 23:12:15 +00:00
Jim Grosbach
d6d4b42ba4 Trivial MC code emitter shell. No instruction forms actually handled yet. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115993 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 22:12:50 +00:00
Jim Grosbach
9af82ba42b Include the auto-generated bits for machine encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115987 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 21:57:55 +00:00
Eric Christopher
df1f5a924e Remember to promote load/store types for stack to register size. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115984 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 21:40:18 +00:00
Jim Grosbach
ae93ed1dd7 ARM instruction don't have instruction prefixes, so remove the helper functions 
for them from the MCCodeEmitter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115975 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 20:41:30 +00:00
Eric Christopher
ee56ea6243 Use the correct register class for load instructions - fixes 
compilation of MultiSource/Benchmarks/Bullet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115907 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 05:50:44 +00:00