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22715 Commits

Author SHA1 Message Date
Elena Demikhovsky
e4092e9895 AVX-512: Optimized BUILD_VECTOR pattern;
fixed encoding of VEXTRACTPS instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201134 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-11 07:25:59 +00:00
Quentin Colombet
defd4bc77b [CodeGenPrepare] Test case for the promotions that bypass the
profitability check due to some other checks in the addressing
mode matcher. I.e., test case for commit r201121.

<rdar://problem/16020230>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201132 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-11 06:55:43 +00:00
Tom Stellard
42faffddb9 R600/SI: Initialize M0 and emit S_WQM_B64 whenever DS instructions are used
DS instructions that access local memory can only uses addresses that
are less than or equal to the value of M0.  When M0 is uninitialized,
then we experience undefined behavior.

This patch also changes the behavior to emit S_WQM_B64 on pixel shaders
no matter what kind of DS instruction is used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201097 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-10 16:58:30 +00:00
Tim Northover
71313f88cb ARM: use natural LLVM IR for vshll instructions
Similarly to the vshrn instructions, these are simple zext/sext + trunc
operations. Using normal LLVM IR should allow for better code, and more sharing
with the AArch64 backend.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201093 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-10 16:20:29 +00:00
Chad Rosier
5fcb5c92d3 [AArch64] Handle aliases of conditional branches without b.pred form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201091 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-10 15:43:11 +00:00
Oliver Stannard
dbd5c285b8 ARM: r12 is callee-saved for interrupt handlers
For A- and R-class processors, r12 is not normally callee-saved, but is for
interrupt handlers. See AAPCS, 5.3.1.1, "Use of IP by the linker".



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201089 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-10 14:24:23 +00:00
Tim Northover
9ed30bb230 ARM: use LLVM IR to represent the vshrn operation
vshrn is just the combination of a right shift and a truncate (and the limits
on the immediate value actually mean the signedness of the shift doesn't
matter). Using that representation allows us to get rid of an ARM-specific
intrinsic, share more code with AArch64 and hopefully get better code out of
the mid-end optimisers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201085 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-10 14:04:07 +00:00
Robert Lougher
5a2ae98407 Test commit - added a new line to vec_shuf-insert.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201083 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-10 12:42:13 +00:00
Matheus Almeida
3f14ca5e30 [mips][msa] Add DLSA instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201081 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-10 12:05:17 +00:00
Matheus Almeida
5f09dd31f0 [mips][msa] Update FileCheck prefix in preparation for
the addition of Mips64 tests.

No functional changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201080 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-10 11:30:09 +00:00
Kostya Serebryany
8cab11a9f8 [asan] support for FreeBSD, LLVM part. patch by Viktor Kutuzov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201067 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-10 07:37:04 +00:00
Elena Demikhovsky
27ef6eec41 AVX-512: Fixed extract_vector_elt for v16i1 and v8i1 vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201066 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-10 07:02:39 +00:00
Craig Topper
ced2756280 Recommit r201059 and r201060 with hopefully a fix for its original failure.
Original commits messages:

Add MRMXr/MRMXm form to X86 for use by instructions which treat the 'reg' field of modrm byte as a don't care value. Will allow for simplification of disassembler code.

Simplify a bunch of code by removing the need for the x86 disassembler table builder to know about extended opcodes. The modrm forms are sufficient to convey the information.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201065 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-10 06:55:41 +00:00
Hao Liu
2825b8f0ea [AArch64]Implement the copy of two FPR8 registers by using FMOVss of two FPR32 registers in copyPhysReg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201061 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-10 03:16:22 +00:00
Benjamin Kramer
275f653307 AsmParser: Parse (and ignore) nested .macro definitions.
This enables a slightly odd feature of gas. The macro is defined when
the outermost macro is instantiated.

PR18599

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201045 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-09 16:22:00 +00:00
Saleem Abdulrasool
91ec991b45 ARM: change attribute tests to use parsed form
This makes the tests more readable by using the -arm-attributes decoding support
in llvm-readobj since that is now available.  Change the invocation commands to
be similar to other test and use a more precise triple (the tests only require
ARM EABI support).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201029 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-08 23:17:02 +00:00
Arnold Schwaighofer
846acbeef1 LoopVectorizer: Keep track of conditional store basic blocks
Before conditional store vectorization/unrolling we had only one
vectorized/unrolled basic block. After adding support for conditional store
vectorization this will not only be one block but multiple basic blocks. The
last block would have the back-edge. I updated the code to use a vector of basic
blocks instead of a single basic block and fixed the users to use the last entry
in this vector. But, I forgot to add the basic blocks to this vector!

Fixes PR18724.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201028 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-08 20:41:13 +00:00
Juergen Ributzka
6f1819f2e6 [Constant Hoisting] Fix insertion point for constant materialization.
The bitcast instruction during constant materialization was not placed correcly
in the presence of phi nodes. This commit fixes the insertion point to be in the
idom instead.

This fixes PR18768

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201009 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-08 00:20:49 +00:00
Rafael Espindola
26baaa1efb Always create a temporary symbol to use with the cfi frame.
This is a small simplification and a small step in fixing pr18743 since
private functions on MachO should be using a 'l' prefix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200994 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-07 21:23:18 +00:00
Rafael Espindola
d413950a93 Use FileCheck variables to simplify this test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200992 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-07 21:11:33 +00:00
Renato Golin
0b9dca0137 Fix Darwin bots from EHABI change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200990 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-07 20:32:32 +00:00
Matt Arsenault
26bc2c8eed R600/SI: Add failing test for 3 x i64 vectors.
Stores of <4 x i64> do work (although they do expand to 4 stores
instead of 2), but 3 x i64 vectors fail to select.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200989 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-07 20:29:40 +00:00
Renato Golin
703197fc94 Remove -arm-disable-ehabi option
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200988 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-07 20:12:49 +00:00
Rafael Espindola
1e75dec97a Don't internalize linkonce_odr non constant variables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200983 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-07 19:04:43 +00:00
Sasa Stankovic
24e5f9652a [mips] Forbid the use of registers t6, t7 and t8 if the target is NaCl.
Differential Revision: http://llvm-reviews.chandlerc.com/D2694



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200978 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-07 17:16:40 +00:00
Rafael Espindola
0732e94378 Fix a bug with .weak_def_can_be_hidden: Mutable variables cannot use it.
Thanks to John McCall for noticing it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200977 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-07 16:21:30 +00:00
Oliver Stannard
c8f5d43820 LLVM-1163: AAPCS-VFP violation when CPRC allocated to stack
According to the AAPCS, when a CPRC is allocated to the stack, all other
VFP registers should be marked as unavailable.

I have also modified the rules for allocating non-CPRCs to the stack, to make
it more explicit that all GPRs must be made unavailable. I cannot think of a
case where the old version would produce incorrect answers, so there is no test
for this.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200970 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-07 11:19:53 +00:00
Sasa Stankovic
fba9c104b9 Changed comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200969 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-07 11:16:02 +00:00
Venkatraman Govindaraju
1826a52645 [Sparc] Add support for parsing synthetic instruction 'mov'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200965 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-07 09:06:52 +00:00
Venkatraman Govindaraju
464d664971 [Sparc] Emit correct encoding for atomic instructions. Also, add support for parsing CAS instructions to test the CAS encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200963 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-07 07:34:49 +00:00
Venkatraman Govindaraju
fabdd6632a [Sparc] Emit relocations for Thread Local Storage (TLS) when integrated assembler is used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200962 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-07 05:54:20 +00:00
Venkatraman Govindaraju
44ad4d00b4 [Sparc] Emit correct relocations for PIC code when integrated assembler is used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200961 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-07 04:24:35 +00:00
Manman Ren
ee5625b3c1 PGO branch weight: fix PR18752.
Fix a bug triggered in IfConverterTriangle when CvtBB has multiple predecessors
by getting the weights before removing a successor.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200958 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-07 00:38:56 +00:00
Jim Grosbach
1f65cfad96 X86: Resolve a long standing FIXME and properly isel pextr[bw].
Generalize the AArch64 .td nodes for AssertZext and AssertSext. Use
them to match the relevant pextr store instructions.

The test widen_load-2.ll requires a slight change because with the
stores gone, the remaining instructions are scheduled in a different
order.

Add test cases for SSE4 and AVX variants.

Resolves rdar://13414672.

Patch by Adam Nemet <anemet@apple.com>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200957 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-07 00:16:33 +00:00
Rafael Espindola
1dd4d5f760 Convert test to FileCheck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200955 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-06 23:35:22 +00:00
Quentin Colombet
30c0f72237 [CodeGenPrepare] Move away sign extensions that get in the way of addressing
mode.

Basically the idea is to transform code like this:
%idx = add nsw i32 %a, 1
%sextidx = sext i32 %idx to i64
%gep = gep i8* %myArray, i64 %sextidx
load i8* %gep

Into:
%sexta = sext i32 %a to i64
%idx = add nsw i64 %sexta, 1
%gep = gep i8* %myArray, i64 %idx
load i8* %gep

That way the computation can be folded into the addressing mode.

This transformation is done as part of the addressing mode matcher.
If the matching fails (not profitable, addressing mode not legal, etc.), the
matcher will revert the related promotions.

<rdar://problem/15519855>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200947 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-06 21:44:56 +00:00
Tom Stellard
226bd876c6 R600/SI: Add a MUBUF store pattern for Reg+Imm offsets
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200935 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-06 18:36:41 +00:00
Tom Stellard
603cd56372 R600/SI: Add a MUBUF store pattern for Imm offsets
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200934 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-06 18:36:39 +00:00
Tom Stellard
becac0f183 R600/SI: Add a MUBUF load pattern for Reg+Imm offsets
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200933 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-06 18:36:38 +00:00
Tom Stellard
22274378d5 R600/SI: Use immediates offsets for SMRD instructions whenever possible
There was a problem with the old pattern, so we were copying some
larger immediates into registers when we could have been encoding
them in the instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200932 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-06 18:36:34 +00:00
Tim Northover
0c245b69f7 X86: add costs for 64-bit vector ext/trunc & rebalance
The most important part of this is probably adding any cost at all for
operations like zext <8 x i8> to <8 x i32>. Before they were being
recorded as extremely costly (24, I believe) which made LLVM fall back
on a 4-wide vectorisation of a loop.

It also rebalances the values for sext, zext and trunc. Lacking any
other sane metric that might work across CPU microarchitectures I went
for instructions. This seems to be in reasonable accord with the rest
of the table (sitofp, ...) though no doubt at least one value is
sub-optimal for some bizarre reason.

Finally, separate AVX and AVX2 values are provided where appropriate.
The CodeGen is quite different in many cases.

rdar://problem/15981990

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200928 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-06 18:18:36 +00:00
Nick Lewycky
44e40408ee A memcpy out of an fresh alloca is a no-op, delete it. Patch by Patrick Walton!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200907 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-06 06:29:19 +00:00
Chandler Carruth
57732bff1e [PM] Add a new "lazy" call graph analysis pass for the new pass manager.
The primary motivation for this pass is to separate the call graph
analysis used by the new pass manager's CGSCC pass management from the
existing call graph analysis pass. That analysis pass is (somewhat
unfortunately) over-constrained by the existing CallGraphSCCPassManager
requirements. Those requirements make it *really* hard to cleanly layer
the needed functionality for the new pass manager on top of the existing
analysis.

However, there are also a bunch of things that the pass manager would
specifically benefit from doing differently from the existing call graph
analysis, and this new implementation tries to address several of them:

- Be lazy about scanning function definitions. The existing pass eagerly
  scans the entire module to build the initial graph. This new pass is
  significantly more lazy, and I plan to push this even further to
  maximize locality during CGSCC walks.
- Don't use a single synthetic node to partition functions with an
  indirect call from functions whose address is taken. This node creates
  a huge choke-point which would preclude good parallelization across
  the fanout of the SCC graph when we got to the point of looking at
  such changes to LLVM.
- Use a memory dense and lightweight representation of the call graph
  rather than value handles and tracking call instructions. This will
  require explicit update calls instead of some updates working
  transparently, but should end up being significantly more efficient.
  The explicit update calls ended up being needed in many cases for the
  existing call graph so we don't really lose anything.
- Doesn't explicitly model SCCs and thus doesn't provide an "identity"
  for an SCC which is stable across updates. This is essential for the
  new pass manager to work correctly.
- Only form the graph necessary for traversing all of the functions in
  an SCC friendly order. This is a much simpler graph structure and
  should be more memory dense. It does limit the ways in which it is
  appropriate to use this analysis. I wish I had a better name than
  "call graph". I've commented extensively this aspect.

This is still very much a WIP, in fact it is really just the initial
bits. But it is about the fourth version of the initial bits that I've
implemented with each of the others running into really frustrating
problms. This looks like it will actually work and I'd like to split the
actual complexity across commits for the sake of my reviewers. =] The
rest of the implementation along with lots of wiring will follow
somewhat more rapidly now that there is a good path forward.

Naturally, this doesn't impact any of the existing optimizer. This code
is specific to the new pass manager.

A bunch of thanks are deserved for the various folks that have helped
with the design of this, especially Nick Lewycky who actually sat with
me to go through the fundamentals of the final version here.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200903 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-06 04:37:03 +00:00
Juergen Ributzka
58bc0ca37b [DAG] Don't pull the binary operation though the shift if the operands have opaque constants.
During DAGCombine visitShiftByConstant assumes that certain binary operations
with only constant operands can always be folded successfully. This is no longer
true when the constant is opaque. This commit fixes visitShiftByConstant by not
performing the optimization for opaque constants. Otherwise we would end up in
an infinite DAGCombine loop.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200900 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-06 04:09:06 +00:00
Manman Ren
c7ac256d52 Set default of inlinecold-threshold to 225.
225 is the default value of inline-threshold. This change will make sure
we have the same inlining behavior as prior to r200886.

As Chandler points out, even though we don't have code in our testing
suite that uses cold attribute, there are larger applications that do
use cold attribute.

r200886 + this commit intend to keep the same behavior as prior to r200886.
We can later on tune the inlinecold-threshold.

The main purpose of r200886 is to help performance of instrumentation based
PGO before we actually hook up inliner with analysis passes such as BPI and BFI.
For instrumentation based PGO, we try to increase inlining of hot functions and
reduce inlining of cold functions by setting inlinecold-threshold.

Another option suggested by Chandler is to use a boolean flag that controls
if we should use OptSizeThreshold for cold functions. The default value
of the boolean flag should not change the current behavior. But it gives us
less freedom in controlling inlining of cold functions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200898 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-06 01:59:22 +00:00
Kevin Enderby
a2f4bb9077 Update the X86 assembler for .intel_syntax to accept
the << and >> bitwise operators.

rdar://15975725


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200896 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-06 01:21:15 +00:00
Paul Robinson
2684ddd72e Disable most IR-level transform passes on functions marked 'optnone'.
Ideally only those transform passes that run at -O0 remain enabled,
in reality we get as close as we reasonably can.
Passes are responsible for disabling themselves, it's not the job of
the pass manager to do it for them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200892 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-06 00:07:05 +00:00
Manman Ren
df7da79db6 Inliner uses a smaller inline threshold for callees with cold attribute.
Added command line option inlinecold-threshold to set threshold for inlining
functions with cold attribute. Listen to the cold attribute when it would
decrease the inline threshold.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200886 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-05 22:53:44 +00:00
Quentin Colombet
1a10a51431 [RegAlloc] Add a last chance recoloring mechanism when everything else failed to
find a register.

The idea is to choose a color for the variable that cannot be allocated and
recolor its interferences around. Unlike the current register allocation scheme,
it is allowed to change the color of an already assigned (but maybe not
splittable or spillable) live interval while propagating this change to its
neighbors.
In other word, there are two things that may help finding an available color:
- Already assigned variables (RS_Done) can be recolored to different color.
- The recoloring allows to catch solutions that needs to touch more that just
  the neighbors of the current allocated variable.

E.g.,
vA can use {R1, R2    }
vB can use {    R2, R3}
vC can use {R1        }
Where vA, vB, and vC cannot be split anymore (they are reloads for instance) and
they all interfere.

vA is assigned R1
vB is assigned R2
vC tries to evict vA but vA is already done.
=> Regular register allocation heuristic fails.

Last chance recoloring kicks in:
vC does as if vA was evicted => vC uses R1.
vC is marked as fixed.
vA needs to find a color.
None are available.
vA cannot evict vC: vC is a fixed virtual register now.
vA does as if vB was evicted => vA uses R2.
vB needs to find a color.
R3 is available.
Recoloring => vC = R1, vA = R2, vB = R3.

<rdar://problem/15947839>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200883 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-05 22:13:59 +00:00
Rafael Espindola
f39297678b Remove support for not using .loc directives.
Clang itself was not using this. The only way to access it was via llc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200862 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-05 18:00:21 +00:00